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公开(公告)号：MY143286A
公开(公告)日：2011-04-15
申请号：MYPI0702154
申请日：1997-05-20
Applicant: PANASONIC CORP
Inventor： HONDA KAZUYOSHI , ODAGIRI MASARU , TAKAHASHI KIYOSHI , ECHIGO NORIYASU , SUNAGARE NOBUKI
Abstract: A METHOD FOR FORMING A THIN FILM INCLUDES THE STEPS OF: SUPPLYING A DEPOSITION MATERIAL IN THE FORM OF A LIQUID ONTO A HEATED SURFACE; HEATING AND VAPORIZING THE DEPOSITION MATERIAL ON THE HEATED SURFACE WHILE THE DEPOSITION MATERIAL IS UNDERGOING MOVEMENT; AND DEPOSITING THE DEPOSITION MATERIAL ONTO A DEPOSITION SURFACE. THE DEPOSITION MATERIAL IS SUPPLIED ONTO A POSITION OF THE HEATED SURFACE WHERE THE VAPORIZED DEPOSITION MATERIAL DOES NOT REACH THE DEPOSITION SURFACE.
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公开(公告)号：DE69841227D1
公开(公告)日：2009-11-19
申请号：DE69841227
申请日：1998-11-16
Applicant: PANASONIC CORP
Inventor： HONDA KAZUYOSHI , ECHIGO NORIYASU , ODAGIRI MASARU , SUNAGARE NOBUKI , SUZAWA SHINICHI
Abstract: The invention relates to a layered product comprising at least 100 deposition units, each unit including: a dielectric layer having a thickness not more than 1µm, and a first metal thin film layer and a second metal thin film layer deposited on one surface of the dielectric layer, the first metal thin film layer and the second metal thin film layer being separated by a belt-shaped electrically insulating portion, wherein deposition positions of the electrically insulating portions of adjacent deposition units are different, and the deposition positions of the electrically insulating portions of every other deposition unit are not the same in the overall layered product. Furthermore, the invention relates to a capacitor formed with the layered product as well as to a method for producing a layered product.
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公开(公告)号：MY139695A
公开(公告)日：2009-10-30
申请号：MYPI0400562
申请日：1997-05-20
Applicant: PANASONIC CORP
Inventor： HONDA KAZUYOSHI , ODAGIRI MASARU , TAKAHASHI KIYOSHI , ECHIGO NORIYASU , SUNAGARE NOBUKI
Abstract: A METHOD FOR FORMING A THIN FILM INCLUDES THE STEPS OF: SUPPLYING A DEPOSITION MATERIAL IN THE FORM OF A LIQUID ONTO A HEATED SURFACE; HEATING AND VAPORIZING THE DEPOSITION MATERIAL ON THE HEATED SURFACE WHILE THE DEPOSITION MATERIAL IS UNDERGOING MOVEMENT; AND DEPOSITING THE DEPOSITION MATERIAL ONTO A DEPOSITION SURFACE. THE DEPOSITION MATERIAL IS SUPPLIED ONTO A POSITION OF THE HEATED SURFACE WHERE THE VAPORIZED DEPOSITION MATERIAL DOES NOT REACH THE DEPOSITION SURFACE.
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公开(公告)号：DE69942885D1
公开(公告)日：2010-12-09
申请号：DE69942885
申请日：1999-06-14
Applicant: PANASONIC CORP
Inventor： HONDA KAZUYOSHI , ECHIGO NORIYASU , ODAGIRI MASARU , SUNAGARE NOBUKI , MIYAKE TORU
IPC: H01G4/30
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Patent Agency Ranking
公开(公告)号：DE69841940D1
公开(公告)日：2010-11-25
申请号：DE69841940
申请日：1998-03-12
Applicant: PANASONIC CORP
Inventor： HONDA KAZUYOSHI , ECHIGO NORIYASU , ODAGIRI MASARU , SUNAGARE NOBUKI
IPC: C23C14/00 , C23C14/04 , C23C14/56 , H01L21/283 , H01L21/3205 , H05K3/00 , H05K3/04 , H05K3/12 , H05K3/14
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公开(公告)号：MY139629A
公开(公告)日：2009-10-30
申请号：MYPI20050892
申请日：2000-04-21
Applicant: PANASONIC CORP
Inventor： HONDA KAZUYOSHI , ECHIGO NORIYASU , ODAGIRI MASARU , SUGIMOTO TAKANORI
IPC: H01G4/30 , H01L21/20 , H01G4/33 , H01G4/38 , H01L21/822 , H01L23/498 , H01L23/50 , H01L27/04 , H05K1/00 , H05K1/02 , H05K1/14 , H05K1/16 , H05K3/00 , H05K3/40 , H05K3/46
Abstract: ELECTRODE LAYERS (1, 2) ARE ARRANGED ON BOTH SIDES OF A DIELECTRIC LAYER (3) FACING EACH OTHER SO AS CONFIGURE A CAPACITOR. LEAD ELECTRODES (4,5) ARE FORMED IN THE ELECTRODE LAYERS (1,2). A PENETRATING ELECTRODE (6) THAT IS INSULATED FROM THE ELECTRODE LAYERS (1,2) IS FORMED. AN ELECTRONIC COMPONENT (10) CONFIGURED IN THIS MANNER IS MOUNTED ON A WIRING BOARD, AND A SEMICONDUCTOR CHIP CAN BE MOUNTED THEREON. ALONG WITH CONNECTING THE SEMICONDUCTOR CHIP TO THE WIRING BOARD VIA THE PENETRATING ELECTRODE (6), THE SEMICONDUCTOR CHIP OR THE WIRING BOARD IS CONNECTED TO THE LEAD ELECTRODES (4,5). IN THIS MANNER, WHILE SUPPRESSING THE SIZE INCREASE OF A MOUNTED AREA, THE CAPACITOR OR THE LIKE CAN BE ARRANGED NEAR THE SEMICONDUCTOR CHIP. THUS, THE SEMICONDUCTOR CHIP IS DRIVEN WITH HIGH FREQUENCY MORE EASILY.
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公开(公告)号：DE10196442B4
公开(公告)日：2011-03-31
申请号：DE10196442
申请日：2001-07-23
Applicant: PANASONIC CORP
Inventor： ECHIGO NORIYASU , HONDA KAZUYOSHI , KAI YOSHIAKI , ODAGIRI MASARU , TACHIHARA HISAAKI , MATSUDA HIDEKI , KATSUBE JUN , IWAOKA KAZUO , SUGIMOTO TAKANORI , SUNAGARE NOBUKI
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公开(公告)号：EP2230680A4
公开(公告)日：2011-06-01
申请号：EP09815448
申请日：2009-12-10
Applicant: PANASONIC CORP
Inventor： HASHIMOTO JUN , GOTOU MASASHI , ECHIGO NORIYASU
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公开(公告)号：JP2010140836A
公开(公告)日：2010-06-24
申请号：JP2008317941
申请日：2008-12-15
Applicant: Panasonic Corp , パナソニック株式会社
Inventor： HASHIMOTO JUN , GOTO SHINJI , ECHIGO NORIYASU
Abstract: PROBLEM TO BE SOLVED: To realize a plasma display panel having a display performance of high definition and high luminance, and with low power consumption. SOLUTION: The PDP includes a front plate 1 in which a dielectric layer 8 is formed so as to cover a display electrode 6 formed on a front glass substrate 3 and a protection layer 9 is formed on the dielectric layer 8 and a rear plate which is arranged opposed to the front plate 1 so as to form a discharge space filled with a discharge gas and has an address electrode in the direction to cross the display electrode 6, and a barrier rib installed to demarcate the discharge space. The protection layer 9 is formed of a metal oxide consisting of magnesium oxide and calcium oxide, and contains zinc, and the metal oxide, in the X-ray diffraction analysis on the protection layer 9, has a peak existing between a diffraction angle in which the peak of magnesium oxide is generated and the diffraction angle in which the peak of calcium oxide is generated. COPYRIGHT: (C)2010,JPO&INPIT
Abstract translation: 要解决的问题：实现具有高清晰度和高亮度的显示性能以及低功耗的等离子体显示面板。 解决方案：PDP包括前板1，其中形成介电层8以覆盖形成在前玻璃基板3上的显示电极6，并且保护层9形成在电介质层8和后部 板，其与前板1相对设置，以形成填充有放电气体的放电空间，并且在与显示电极6交叉的方向上具有寻址电极，以及设置用于限定放电空间的隔板。 保护层9由氧化镁和氧化钙组成的金属氧化物形成，含有锌，金属氧化物在保护层9的X射线衍射分析中具有峰值， 产生氧化镁的峰值，产生氧化钙峰的衍射角。 版权所有（C）2010，JPO＆INPIT
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