公开(公告)号：DE10196442B4

公开(公告)日：2011-03-31

申请号：DE10196442

申请日：2001-07-23

Applicant: PANASONIC CORP

Inventor： ECHIGO NORIYASU ,  HONDA KAZUYOSHI ,  KAI YOSHIAKI ,  ODAGIRI MASARU ,  TACHIHARA HISAAKI ,  MATSUDA HIDEKI ,  KATSUBE JUN ,  IWAOKA KAZUO ,  SUGIMOTO TAKANORI ,  SUNAGARE NOBUKI

IPC: C07C323/12 ,  C08F2/00 ,  C08F16/36 ,  C08F20/38 ,  C08F22/24 ,  C08F28/02 ,  C08L29/12 ,  C08L33/14 ,  C08L41/00 ,  H01B3/30 ,  H01B3/44 ,  H01C7/00 ,  H01C17/065 ,  H01G4/018 ,  H01G4/18 ,  H01G4/30

公开(公告)号：MY139629A

公开(公告)日：2009-10-30

申请号：MYPI20050892

申请日：2000-04-21

Applicant: PANASONIC CORP

Inventor： HONDA KAZUYOSHI ,  ECHIGO NORIYASU ,  ODAGIRI MASARU ,  SUGIMOTO TAKANORI

IPC: H01G4/30 ,  H01L21/20 ,  H01G4/33 ,  H01G4/38 ,  H01L21/822 ,  H01L23/498 ,  H01L23/50 ,  H01L27/04 ,  H05K1/00 ,  H05K1/02 ,  H05K1/14 ,  H05K1/16 ,  H05K3/00 ,  H05K3/40 ,  H05K3/46

Abstract: ELECTRODE LAYERS (1, 2) ARE ARRANGED ON BOTH SIDES OF A DIELECTRIC LAYER (3) FACING EACH OTHER SO AS CONFIGURE A CAPACITOR. LEAD ELECTRODES (4,5) ARE FORMED IN THE ELECTRODE LAYERS (1,2). A PENETRATING ELECTRODE (6) THAT IS INSULATED FROM THE ELECTRODE LAYERS (1,2) IS FORMED. AN ELECTRONIC COMPONENT (10) CONFIGURED IN THIS MANNER IS MOUNTED ON A WIRING BOARD, AND A SEMICONDUCTOR CHIP CAN BE MOUNTED THEREON. ALONG WITH CONNECTING THE SEMICONDUCTOR CHIP TO THE WIRING BOARD VIA THE PENETRATING ELECTRODE (6), THE SEMICONDUCTOR CHIP OR THE WIRING BOARD IS CONNECTED TO THE LEAD ELECTRODES (4,5). IN THIS MANNER, WHILE SUPPRESSING THE SIZE INCREASE OF A MOUNTED AREA, THE CAPACITOR OR THE LIKE CAN BE ARRANGED NEAR THE SEMICONDUCTOR CHIP. THUS, THE SEMICONDUCTOR CHIP IS DRIVEN WITH HIGH FREQUENCY MORE EASILY.