公开(公告)号：IL318195A

公开(公告)日：2025-03-01

申请号：IL31819525

申请日：2025-01-06

Applicant: PANASONIC IP CORP AMERICA ,  GAO JINGYING ,  TEO HAN BOON ,  LIM CHONG SOON ,  YADAV PRAVEEN KUMAR ,  ABE KIYOFUMI ,  NISHI TAKAHIRO ,  TOMA TADAMASA

Inventor： GAO JINGYING ,  TEO HAN BOON ,  LIM CHONG SOON ,  YADAV PRAVEEN KUMAR ,  ABE KIYOFUMI ,  NISHI TAKAHIRO ,  TOMA TADAMASA

Abstract: An image decoder includes circuitry and a memory connected to the circuitry. In operation, the circuitry decodes a first bitstream to acquire a first image, decodes a second bitstream to acquire specification information specifying a particular region in the first image and a second image containing image data for the particular region, and generates a third image based on the first image, the specification information, and the second image.

公开(公告)号：AU2023304865A1

公开(公告)日：2025-01-09

申请号：AU2023304865

申请日：2023-07-03

Applicant: PANASONIC IP CORP AMERICA

Inventor： TEO HAN BOON ,  GAO JINGYING ,  LIM CHONG SOON ,  YADAV PRAVEEN KUMAR ,  ABE KIYOFUMI ,  NISHI TAKAHIRO ,  TOMA TADAMASA

IPC: H04N19/70 ,  H04N19/82

Abstract: A decoding device (200) comprises a circuit and a memory connected to the circuit, the circuit executing the operations of: decoding a plurality of neural network information sets each identifying a neural network filter (S601); decoding, from one access unit, two or more activation information sets each specifying one of the plurality of neural network information sets (S602); and applying, to one picture, two or more neural network filters identified by two or more neural network information sets specified by the two or more activation information sets (S603).

公开(公告)号：AU2023306696A2

公开(公告)日：2025-03-27

申请号：AU2023306696

申请日：2023-06-01

Applicant: PANASONIC IP CORP AMERICA

Inventor： GAO JINGYING ,  TEO HAN BOON ,  LIM CHONG SOON ,  YADAV PRAVEEN KUMAR ,  ABE KIYOFUMI ,  NISHI TAKAHIRO ,  TOMA TADAMASA

IPC: H04N19/30 ,  H04N19/46 ,  H04N19/85

Abstract: The present invention is provided with: a circuit; and a memory connected to the circuit. In operation, the circuit decodes a first bitstream to acquire a first image, decodes a second bitstream to acquire specification information specifying a specific region in the first image and a second image including image data of the specific region, and generates a third image on the basis of the first image, the specification information, and the second image.

公开(公告)号：AU2023306696A1

公开(公告)日：2025-01-23

申请号：AU2023306696

申请日：2023-06-01

Applicant: PANASONIC IP CORP AMERICA

Inventor： GAO JINGYING ,  TEO HAN BOON ,  LIM CHONG SOON ,  YADAV PRAVEEN KUMAR ,  ABE KIYOFUMI ,  NISHI TAKAHIRO ,  TOMA TADAMASA

IPC: H04N19/30 ,  H04N19/46 ,  H04N19/85

Abstract: The present invention is provided with: a circuit; and a memory connected to the circuit. In operation, the circuit decodes a first bitstream to acquire a first image, decodes a second bitstream to acquire specification information specifying a specific region in the first image and a second image including image data of the specific region, and generates a third image on the basis of the first image, the specification information, and the second image.