公开(公告)号：US20200243644A1

公开(公告)日：2020-07-30

申请号：US16750292

申请日：2020-01-23

Applicant: POSTECH Research and Business Development Foundation

Inventor： Rock Hyun BAEK ,  Jun Sik YOON ,  Jin Su JEONG ,  Seung Hwan LEE

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

Abstract: Disclosed is a field effect transistor including an insulating film disposed between a source/drain region and a substrate. Since the insulating film prevents current leakage under a channel, it is not necessary to form a punch-through stopper. Further disclosed is a method of forming a field effect transistor.

公开(公告)号：US20220085781A1

公开(公告)日：2022-03-17

申请号：US17387876

申请日：2021-07-28

Applicant: POSTECH Research and Business Development Foundation

Inventor： Rock Hyun BAEK ,  Jun Sik YOON

IPC: H03G3/30 ,  H03F3/21 ,  H03F3/193 ,  H03F3/45

Abstract: Disclosed in a CASCODE device in which multiple transistors are stacked in a vertical direction and connected in series. The CASCODE device exhibits improvements in device/circuit intrinsic gain (GmRo) that is a performance index for analog/RF applications, cutoff frequency (Ft), and maximum oscillation frequency (Fmax). A method of manufacturing the CASCODE device is also disclosed.

公开(公告)号：US20250148261A1

公开(公告)日：2025-05-08

申请号：US18622741

申请日：2024-03-29

Applicant: RESEARCH COOPERATION FOUNDATION OF YEUNGNAM UNIVERSITY ,  POSTECH RESEARCH AND BUSINESS DEVELOPMENT FOUNDATION

Inventor： Hyun Chul CHOI ,  Jeong Sik LEE ,  Rock Hyun BAEK ,  Kyeong Rae CHO

IPC: G06N3/042

Abstract: Disclosed are a cell-level analysis method of a memory and a computing device for performing the same. The cell-level analysis method of a memory is a cell-level analysis method of a memory that is executed in a computing device including one or more processors and a memory storing one or more programs executed by the one or more processors, the cell-level analysis method including acquiring information on a location of each cell in the memory, generating graph-structured data for a target cell based on the location of each cell in the memory, and training a graph neural network model to predict one or more of an electrical characteristic of the target cell and a program and verify level (PV level) of the target cell by inputting the graph-structured data into the graph neural network model.

公开(公告)号：US20220277189A1

公开(公告)日：2022-09-01

申请号：US17551450

申请日：2021-12-15

Applicant: RESEARCH COOPERATION FOUNDATION OF YEUNGNAM UNIVERSITY ,  POSTECH Research and Business Development Foundation

Inventor： Hyun Chul CHOI ,  Rock Hyun BAEK ,  Jun Sik YOON ,  Hyeok YUN

IPC: G06N3/063 ,  G06N3/08 ,  G06N3/04 ,  G03F7/20

Abstract: A method for setting of a semiconductor manufacturing parameter according to an embodiment is a method performed in a computing device including one or more processors, and a memory for storing one or more programs executed by the one or more processors, the method including an operation of inputting manufacturing parameters for manufacturing a semiconductor to a neural network model and an operation of training the neural network model to predict at least one of power and delay of the semiconductor based on the input manufacturing parameters.

公开(公告)号：US20250139345A1

公开(公告)日：2025-05-01

申请号：US18814380

申请日：2024-08-23

Applicant: RESEARCH COOPERATION FOUNDATION OF YEUNGNAM UNIVERSITY ,  POSTECH RESEARCH AND BUSINESS DEVELOPMENT FOUNDATION

Inventor： Hyun Chul CHOI ,  Chang Hyeon AN ,  Rock Hyun BAEK ,  Hyeok YUN

IPC: G06F30/337 ,  G06F119/06 ,  G06F119/18

Abstract: A machine-learning method for semiconductor process optimization may include inputting semiconductor-related parameters into each of first neural network models and outputting, based on the semiconductor-related parameters, a predicted figure of merit of a semiconductor device as a first output value from each of the first neural network models. After a semiconductor manufacturing process is performed with a semiconductor manufacturing parameter, electrical measurement parameter values may be measured using one or more measuring devices. The semiconductor-related parameters may include electrical measurement parameter values measured on one or more semiconductor devices. The method may also utilize a feedback loop between an output and an input of the first neural network models so that the electrical measurement parameter values can be updated based on an output value of the first neural network models. A second neural network model may also be used. A computing device and a system are also disclosed.

公开(公告)号：US20230274985A1

公开(公告)日：2023-08-31

申请号：US17983319

申请日：2022-11-08

Applicant: POSTECH Research and Business Development Foundation

Inventor： Rock Hyun BAEK ,  Hyeok YUN

IPC: H01L21/66 ,  G06N3/08

CPC classification number: H01L22/14 ,  G06N3/08 ,  H01L22/12 ,  H01L22/20

Abstract: Disclosed are a method and apparatus for setting a semiconductor parameter. The method for setting a semiconductor parameter according to an embodiment of the present disclosure is a method performed on a computing apparatus including one or more processors and a memory storing one or more programs executed by the one or more processors, the method including acquiring electrical measurement parameters corresponding to preset semiconductor manufacturing parameters, classifying the electrical measurement parameters into a plurality of groups according to a degree of correlation, extracting a correlation axis reflecting a correlation between electrical measurement parameters belonging to a corresponding group for each classified group, and predicting a figure of merit of a semiconductor device by using data values of electrical measurement parameters belonging to the corresponding group as input based on the correlation axis of each group.

公开(公告)号：US20230100196A1

公开(公告)日：2023-03-30

申请号：US18071876

申请日：2022-11-30

Applicant: POSTECH Research and Business Development Foundation

Inventor： Rock Hyun BAEK ,  Jun Sik YOON ,  Jin Su JEONG ,  Seung Hwan LEE

IPC: H01L29/08 ,  H01L29/10 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

Abstract: Disclosed is a fin field-effect transistor having size-reduced source/drain regions so that a merging phenomenon of epitaxial structures between transistors in a layout is prevented, thus increasing the number of transistors per unit area, and so that an additional mask process is not required, thus maintain processing costs without change, and a method of manufacturing the same.