公开(公告)号：US20150138656A1

公开(公告)日：2015-05-21

申请号：US14546201

申请日：2014-11-18

Applicant: Point Engineering Co., Ltd.

Inventor： Bum Mo Ahn ,  Ki Myung Nam ,  Young Chul Jun

IPC: H05K1/02 ,  G02B7/02

CPC classification number: H05K1/0274 ,  G02B7/02 ,  H05K2201/10106 ,  H05K2201/10121

Abstract: A chip substrate includes: a conductive layer being stacked in one direction and constituting a chip substrate; an insulator being alternately stacked with the conductive layer and electrically separating the conductive layer; and a lens insert having: a depression reaching down to a predetermined depth from a specified area of an upper surface of the chip substrate overlapping with the insulator; and a predetermined number of sides on the upper surface wherein arcs are formed at regions where the sides are met with each other. Since the space for inserting a lens can be formed to have a shape comprising straight lines, and a lens to be inserted can also be manufactured in a shape comprising straight lines, therefore the manufacturing process for a lens to be inserted into the chip substrate can be further simplified.

Abstract translation: 芯片基板包括：导电层沿一个方向堆叠并构成芯片基板; 绝缘体与所述导电层交替堆叠并电分离所述导电层; 以及透镜插入件，其具有：从与所述绝缘体重叠的所述芯片基板的上表面的规定区域到达预定深度的凹陷; 并且在上表面上具有预定数量的边，其中在相互满足边的区域处形成弧。 由于用于插入透镜的空间可以形成为具有包括直线的形状，并且也可以制造具有直线的形状的待插入的透镜，因此用于插入到芯片基板的透镜的制造工艺可以 进一步简化。

公开(公告)号：US20150243864A1

公开(公告)日：2015-08-27

申请号：US14418966

申请日：2013-08-01

Applicant: Point Engineering Co., Ltd.

Inventor： Bum Mo Ahn ,  Ki Myung Nam ,  Young Chul Jun

IPC: H01L33/64 ,  H01L33/00 ,  H01L33/44 ,  H01L33/62

CPC classification number: H01L33/644 ,  H01L24/97 ,  H01L25/0753 ,  H01L33/0095 ,  H01L33/62 ,  H01L33/647 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2924/181 ,  H01L2933/0066 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: The present invention relates to a method for manufacturing an optical device and to an optical device manufactured by the method, in which heat-dissipating performance by a heat sink and thermal insulation performance between a substrate and the heat sink are improved and workability is enhanced. According to a first characteristic of the present invention, the method for manufacturing an optical device comprises: (a) a step of preparing a disk for an optical device having a vertical thermal insulation layer; (b) a step of forming a groove along a cut line formed on the lower surface of the disk for an optical device; (c) a step of applying liquid insulation material to the surface on which the groove is formed and hardening the liquid insulation material to form an electrically insulating layer having a planar surface; and (d) a step of forming a fixing hole penetrating in a vertical direction through both the disk for an optical device and the groove.

Abstract translation: 本发明涉及一种制造光学元件的方法和通过该方法制造的光学器件的方法，其中通过散热器的散热性能和衬底与散热器之间的绝热性能得到提高，并且可操作性得到提高。 根据本发明的第一特征，光学装置的制造方法包括：（a）制备具有垂直绝热层的光学装置的盘的步骤; （b）沿着形成在用于光学装置的盘的下表面上的切割线形成凹槽的步骤; （c）将液体绝缘材料施加到其上形成有槽的表面的步骤，并使所述液体绝缘材料硬化以形成具有平坦表面的电绝缘层; 以及（d）形成沿垂直方向穿过光盘装置盘和凹槽的固定孔的步骤。

公开(公告)号：US20140225135A1

公开(公告)日：2014-08-14

申请号：US14343674

申请日：2012-07-26

Applicant: Point Engineering Co., LTD

Inventor： Bum Mo Ahn ,  Ki Myung Nam ,  Young Chul Jun

IPC: H01L33/64

CPC classification number: H01L33/648 ,  H01L23/3677 ,  H01L23/4006 ,  H01L23/4093 ,  H01L33/642 ,  H01L2224/73265 ,  H01L2933/0075

Abstract: The present invention relates to an optical device array substrate having a built-in heat dissipating structure, and to a method for manufacturing same, wherein the optical device array substrate itself is used as a heat sink and a coupling hole is formed at the bottom of the substrate to have a heat dissipating rod coupled thereto. The optical device array substrate having a built-in heat dissipating structure of the present invention consists essentially of: an optical device array substrate having a plurality of optical devices arranged on the top surface thereof and a plurality of coupling holes formed in the bottom surface thereof; and rod-shaped heat dissipating rods that have coupling projections formed on upper ends thereof, and are coupled to each of the coupling holes. In the above-described structure, the coupling holes are threaded, and the coupling projections are also threaded so as to be screw-coupled to the coupling holes. The coupling holes are formed having a downwardly narrowing taper, and the coupling projections are formed having a downwardly narrowing taper so as to be precisely coupled with the coupling holes even when in a contracted state under sub-freezing temperatures. The surfaces of the heat dissipating rods are characterized in that insulation coating layers are formed thereon and not on the coupling projections. A portion of the insulation coating layers on some of the heat dissipating rods may be removed to function as electrodes.

Abstract translation: 本发明涉及具有内置散热结构的光学元件阵列基板及其制造方法，其中光学元件阵列基板本身用作散热器，并且在底部形成有耦合孔 所述基板具有耦合到其上的散热杆。 具有本发明的内置散热结构的光学元件阵列基板主要由以下部分组成：具有设置在其顶面上的多个光学元件的光学元件阵列基板和形成在其底面的多个连接孔 ; 杆状散热杆，其上部形成有联接突起，并且联接到每个连接孔。 在上述结构中，联接孔是螺纹连接的，并且联接突起也是螺纹连接的，以便联接到联接孔。 联接孔形成为具有向下变窄的锥形，并且联接突起形成为具有向下变窄的锥形，以便即使在亚冷冻温度下处于收缩状态下也能与联接孔精确耦合。 散热棒的表面的特征在于其上形成有绝缘涂层，而不在耦合突起上。 一些散热棒上的绝缘涂层的一部分可以被去除以用作电极。

公开(公告)号：US09537074B2

公开(公告)日：2017-01-03

申请号：US14609112

申请日：2015-01-29

Applicant: Point Engineering Co., Ltd.

Inventor： Ki Myung Nam ,  Tae Hwan Song ,  Young Chul Jun

IPC: B29C65/00 ,  B32B3/00 ,  B32B5/00 ,  B32B5/18 ,  B32B37/00 ,  H05K3/46 ,  B32B38/04 ,  C09J5/02 ,  B32B27/00 ,  B32B7/00 ,  B32B9/00 ,  B32B15/04 ,  B32B15/08 ,  B32B27/38 ,  H01L29/18 ,  H01L33/00 ,  H01L33/64 ,  H01L23/00 ,  H01L33/48 ,  H01L25/00 ,  B32B15/092 ,  B32B15/20 ,  B32B27/04 ,  B29C65/48 ,  H01L33/62

CPC classification number: H01L33/641 ,  B29C65/4835 ,  B32B15/092 ,  B32B15/20 ,  B32B27/04 ,  B32B2255/06 ,  B32B2255/26 ,  B32B2260/046 ,  H01L24/97 ,  H01L25/50 ,  H01L33/005 ,  H01L33/483 ,  H01L33/486 ,  H01L33/62 ,  H01L33/644 ,  H01L33/647 ,  H01L2224/73265 ,  H01L2924/12041 ,  H01L2933/0066 ,  H01L2933/0075 ,  Y10T428/24612 ,  Y10T428/31522 ,  Y10T428/31678

Abstract: An optical device substrate includes metal plates and insulating layers formed between the metal plates. Each insulating layer includes a cured insulating layer formed by curing insulating material and an anodized layer merged with each metal plate, the anodized layer formed by anodizing a first metal and a second metal of each metal plate. The first metal and the second metal include a first anodized layer and a second anodized layer, respectively, and are electrically insulated by interfaces including a first interface formed between the first metal and the first anodized layer, a second interface formed between the first anodized layer and the cured insulating layer, a third interface formed between the cured insulating layer and the second metal and a fourth interface formed between the second anodized layer and the second metal.

Abstract translation: 光学元件基板包括金属板和形成在金属板之间的绝缘层。 每个绝缘层包括通过固化绝缘材料形成的固化绝缘层和与每个金属板合并的阳极氧化层，阳极氧化层通过阳极氧化每个金属板的第一金属和第二金属而形成。 第一金属和第二金属分别包括第一阳极氧化层和第二阳极氧化层，并且通过界面电绝缘，所述界面包括形成在第一阳极氧化层和第一阳极氧化层之间的第一界面，形成在第一阳极氧化层 固化的绝缘层，形成在固化的绝缘层和第二金属之间的第三界面和形成在第二阳极氧化层和第二金属之间的第四界面。

公开(公告)号：US20150147580A1

公开(公告)日：2015-05-28

申请号：US14609112

申请日：2015-01-29

Applicant: Point Engineering Co., Ltd.

Inventor： Ki Myung Nam ,  Tae Hwan Song ,  Young Chul Jun

IPC: H01L33/64

CPC classification number: H01L33/641 ,  B29C65/4835 ,  B32B15/092 ,  B32B15/20 ,  B32B27/04 ,  B32B2255/06 ,  B32B2255/26 ,  B32B2260/046 ,  H01L24/97 ,  H01L25/50 ,  H01L33/005 ,  H01L33/483 ,  H01L33/486 ,  H01L33/62 ,  H01L33/644 ,  H01L33/647 ,  H01L2224/73265 ,  H01L2924/12041 ,  H01L2933/0066 ,  H01L2933/0075 ,  Y10T428/24612 ,  Y10T428/31522 ,  Y10T428/31678

Abstract: An optical device substrate includes metal plates and insulating layers formed between the metal plates. Each insulating layer includes a cured insulating layer formed by curing insulating material and an anodized layer merged with each metal plate, the anodized layer formed by anodizing a first metal and a second metal of each metal plate. The first metal and the second metal include a first anodized layer and a second anodized layer, respectively, and are electrically insulated by interfaces including a first interface formed between the first metal and the first anodized layer, a second interface formed between the first anodized layer and the cured insulating layer, a third interface formed between the cured insulating layer and the second metal and a fourth interface formed between the second anodized layer and the second metal.

Abstract translation: 光学元件基板包括金属板和形成在金属板之间的绝缘层。 每个绝缘层包括通过固化绝缘材料形成的固化绝缘层和与每个金属板合并的阳极氧化层，阳极氧化层通过阳极氧化每个金属板的第一金属和第二金属而形成。 第一金属和第二金属分别包括第一阳极氧化层和第二阳极氧化层，并且通过界面电绝缘，所述界面包括形成在第一阳极氧化层和第一阳极氧化层之间的第一界面，形成在第一阳极氧化层 固化的绝缘层，形成在固化的绝缘层和第二金属之间的第三界面和形成在第二阳极氧化层和第二金属之间的第四界面。

公开(公告)号：US09847462B2

公开(公告)日：2017-12-19

申请号：US14525478

申请日：2014-10-28

Applicant: Point Engineering Co., Ltd.

Inventor： Ki Myung Nam ,  Seung Ho Park ,  Young Chul Jun

IPC: H01L33/48 ,  H01L23/00

CPC classification number: H01L33/486 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2924/12041 ,  H01L2933/0033 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Provided is an array substrate for mounting a chip. The array substrate includes a plurality of conductive layers unidirectionally stacked with respect to an original chip substrate; a plurality of insulating layers alternately stacked with the plurality of conductive layers, and electrically separate the plurality of conductive layers; and a cavity having a groove of a predetermined depth with respect to a region including the plurality of insulating layers in an upper surface of the original chip substrate. Accordingly, since the optical device array of a single structure is used as a line source of light, an emission angle emitted from the optical device is great, it is not necessary to form an interval for supplying an amount of light, and a display device can be simply constructed. Further, since it is not necessary to perform soldering a plurality of LED packages on a printed circuit board, a thickness of a back light unit can be reduced.

公开(公告)号：US09374890B2

公开(公告)日：2016-06-21

申请号：US14546201

申请日：2014-11-18

Applicant: Point Engineering Co., Ltd.

Inventor： Bum Mo Ahn ,  Ki Myung Nam ,  Young Chul Jun

IPC: G02B7/02 ,  G02B3/00 ,  H05K1/02

CPC classification number: H05K1/0274 ,  G02B7/02 ,  H05K2201/10106 ,  H05K2201/10121

Abstract: A chip substrate includes: a conductive layer being stacked in one direction and constituting a chip substrate; an insulator being alternately stacked with the conductive layer and electrically separating the conductive layer; and a lens insert having: a depression reaching down to a predetermined depth from a specified area of an upper surface of the chip substrate overlapping with the insulator; and a predetermined number of sides on the upper surface wherein arcs are formed at regions where the sides are met with each other. Since the space for inserting a lens can be formed to have a shape comprising straight lines, and a lens to be inserted can also be manufactured in a shape comprising straight lines, therefore the manufacturing process for a lens to be inserted into the chip substrate can be further simplified.

Abstract translation: 芯片基板包括：导电层沿一个方向堆叠并构成芯片基板; 绝缘体与所述导电层交替堆叠并电分离所述导电层; 以及透镜插入件，其具有：从与所述绝缘体重叠的所述芯片基板的上表面的规定区域到达预定深度的凹陷; 并且在上表面上具有预定数量的边，其中在相互满足边的区域处形成弧。 由于用于插入透镜的空间可以形成为具有包括直线的形状，并且也可以制造具有直线的形状的待插入的透镜，因此用于插入到芯片基板的透镜的制造工艺可以 进一步简化。

公开(公告)号：US20150115310A1

公开(公告)日：2015-04-30

申请号：US14525478

申请日：2014-10-28

Applicant: Point Engineering Co., Ltd.

Inventor： Ki Myung Nam ,  Seung Ho Park ,  Young Chul Jun

IPC: H01L33/48

CPC classification number: H01L33/486 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2924/12041 ,  H01L2933/0033 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Provided is an array substrate for mounting a chip. The array substrate includes a plurality of conductive layers unidirectionally stacked with respect to an original chip substrate; a plurality of insulating layers alternately stacked with the plurality of conductive layers, and electrically separate the plurality of conductive layers; and a cavity having a groove of a predetermined depth with respect to a region including the plurality of insulating layers in an upper surface of the original chip substrate. Accordingly, since the optical device array of a single structure is used as a line source of light, an emission angle emitted from the optical device is great, it is not necessary to form an interval for supplying an amount of light, and a display device can be simply constructed. Further, since it is not necessary to perform soldering a plurality of LED packages on a printed circuit board, a thickness of a back light unit can be reduced.

Abstract translation: 提供了一种用于安装芯片的阵列基板。 阵列基板包括相对于原始芯片基板单向堆叠的多个导电层; 多个绝缘层，与所述多个导电层交替堆叠，并且电分离所述多个导电层; 以及具有相对于在原始芯片衬底的上表面中包括多个绝缘层的区域具有预定深度的凹槽的空腔。 因此，由于将单一结构的光学元件阵列用作线光源，所以从光学器件发射的发射角大，不需要形成用于提供光量的间隔，并且显示装置 可以简单地构建。 此外，由于不需要在印刷电路板上进行多个LED封装的焊接，所以可以减小背光单元的厚度。