中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

11 records (took 0.021 seconds)

    REINICIO Y ACTIVACIÓN EN BANDA EN UN BUS DE AUDIO DIFERENCIAL
    2.
    发明专利
    REINICIO Y ACTIVACIÓN EN BANDA EN UN BUS DE AUDIO DIFERENCIAL 未知

    公开(公告)号：AR113041A1

    公开(公告)日：2020-01-22

    申请号：ARP180102503

    申请日：2018-09-04

    Applicant: QUALCOMM INC

    Inventor： GIL AMIT ,  AMARILIO LIOR

    IPC: G06F13/362 ,  G06F3/16

    Abstract: Sistemas y métodos para el reinicio y activación en banda en un bus de audio diferencial. En particular, después de entrar en un modo de baja potencia, un dispositivo maestro abre un drenaje en un transistor que dirige el bus de audio diferencial. Cuando un dispositivo esclavo necesita que el bus se active, el dispositivo esclavo puede hacer la transición del estado del bus. Al detectar la transición del bus, el dispositivo maestro puede reafirmar el control del estado del bus y mantener el bus en este nuevo estado hasta que esté listo para emitir una secuencia de sincronización. Asimismo, un aspecto adicional de la presente descripción proporciona una secuencia distintiva de mantenimiento del bus en un estado predefinido por una duración prolongada interrumpida mediante una inversión relativamente breve del estado que desencadena un reinicio de todos los dispositivos esclavos en el bus de audio.

    Comunicación de audio multicanal en un sistema de bus multimedia inter-chip serie de baja potencia (SLIMbus)
    4.
    发明专利
    Comunicación de audio multicanal en un sistema de bus multimedia inter-chip serie de baja potencia (SLIMbus) 未知

    公开(公告)号：ES2706307T3

    公开(公告)日：2019-03-28

    申请号：ES15763748

    申请日：2015-09-02

    Applicant: QUALCOMM INC

    Inventor： AMARILIO LIOR ,  BALATSOS ARIS

    IPC: G06F13/42 ,  G06F13/28

    Abstract: Una fuente de audio que comprende: un puerto de salida multicanal (302(X)) configurado para ser acoplado a un bus (320) de multiplexado por división de tiempo, TDM, que comprende un bus multimedia inter-chip serie de baja potencia, SLIMbus, en la que el puerto de salida multicanal está configurado para conectarse simultáneamente a, al menos, dos canales de datos (316L, 318R) transportados por el bus TDM; y un conducto de datos (308) acoplado al puerto de salida multicanal y configurado para pasar datos de audio entrelazados (306) al puerto de salida multicanal.

    Power reduction through clock management
    5.
    发明专利
    Power reduction through clock management 未知

    公开(公告)号：AU2016270383A1

    公开(公告)日：2017-11-09

    申请号：AU2016270383

    申请日：2016-05-09

    Applicant: QUALCOMM INC

    Inventor： KHAZIN ALEXANDER ,  AMARILIO LIOR

    IPC: G06F1/08 ,  G06F1/32 ,  H04R3/00

    Abstract: Power reduction through clock management techniques are disclosed. In one aspect, the clock management is applied to a clock signal on a SOUNDWIRE™ communication bus. In particular, a control system associated with a master device on the communication bus may evaluate frequency requirements of audio streams on the communication bus and select a lowest possible clock frequency that meets the frequency requirements. Lower clock frequencies result in fewer clock transitions and result in a net power saving relative to higher clock frequencies. In the event of a clock frequency change, the master device communicates the clock frequency that will be used prospectively to slave devices on the communication bus, and all devices transition to the new frequency at the same frame boundary. In addition to the power savings, exemplary aspects of the present disclosure do not impact an active audio stream.

    SYSTEMS AND METHODS FOR HANDLING SILENCE IN AUDIO STREAMS
    6.
    发明专利
    SYSTEMS AND METHODS FOR HANDLING SILENCE IN AUDIO STREAMS 未知

    公开(公告)号：CA3015837A1

    公开(公告)日：2017-10-05

    申请号：CA3015837

    申请日：2017-03-03

    Applicant: QUALCOMM INC

    Inventor： AMARILIO LIOR ,  GIL AMIT ,  SCHNITZER ODED

    IPC: G10L19/16 ,  G06F3/16 ,  G06F13/38 ,  G10L19/012 ,  H03G3/34

    Abstract: Systems and methods for handling silence in audio streams are disclosed. In one aspect, a transmitter detects a halt in an audio stream. After detection of the halt in the audio stream, the transmitter embeds a silence signal into the audio stream and transmits the silence signal to associated receivers. The associated receivers may respond to the embedded silence signal by "playing" silence or by using the silence signal to activate a silence protocol. In either event, the associated receivers do not receive the original audio halt and do not produce an unwanted audio artifact.

    Multi-channel audio communication in a serial low-power inter-chip media bus (slimbus) system
    7.
    发明专利
    Multi-channel audio communication in a serial low-power inter-chip media bus (slimbus) system 未知

    公开(公告)号：AU2015312023A1

    公开(公告)日：2017-02-23

    申请号：AU2015312023

    申请日：2015-09-02

    Applicant: QUALCOMM INC

    Inventor： AMARILIO LIOR ,  BALATSOS ARIS

    IPC: G06F13/42 ,  G06F13/28

    Abstract: Multi-channel audio communication in a Serial Low-power Inter-chip Media Bus (SLIMbus) system (300) is disclosed. A multi-channel output port (302(X)) is provided in a SLIMbus system. The multi-channel output port receives an audio stream from an audio source (e.g., a storage medium) via a direct memory access (DMA) pipe (308) and distributes the audio stream to multiple receiving ports (234,238) (e.g., speakers) over multiple data channels (316L,318R), all connected to the single multi-channel output port. A multi-channel input port is also provided in the SLIMbus system. The multi-channel input port connects to multiple data channels from multiple distributing ports (e.g., microphones). It is thereby possible to support multiple data channels with a single DMA pipe, thus improving implementation flexibilities and efficiencies of the SLIMbus system.

    DEVICE IDENTIFICATION GENERATION IN ELECTRONIC DEVICES TO ALLOW EXTERNAL CONTROL OF DEVICE IDENTIFICATION FOR BUS COMMUNICATIONS IDENTIFICATION, AND RELATED SYSTEMS AND METHODS
    8.
    发明专利
    DEVICE IDENTIFICATION GENERATION IN ELECTRONIC DEVICES TO ALLOW EXTERNAL CONTROL OF DEVICE IDENTIFICATION FOR BUS COMMUNICATIONS IDENTIFICATION, AND RELATED SYSTEMS AND METHODS 未知

    公开(公告)号：CA2935766A1

    公开(公告)日：2015-08-06

    申请号：CA2935766

    申请日：2015-02-02

    Applicant: QUALCOMM INC

    Inventor： AMARILIO LIOR ,  AMON YOSSI ,  GERBER NIR ,  SHACHAM ASSAF

    IPC: H04L29/12 ,  G06F13/42

    Abstract: Device identification generation in electronic devices to allow external control, such as selection or reprogramming, of device identification for bus communications identification, is disclosed. In this manner, device identifications of electronic devices coupled to a common communications bus in a system can be selected or reprogrammed to ensure they are unique to avoid bus communications collisions. In certain aspects, to select or reprogram a device identification in an electronic device, an external source can be electrically coupled to the electronic device. The external source closes a circuit with a device identification generation circuit in the electronic device. The closed circuit provides a desired electrical characteristic detectable by the device identification generation circuit. The device identification generation circuit is configured to generate a device identification as a function of the detected electrical characteristics of the closed circuit from the external source.

    DELAY CIRCUITS AND RELATED SYSTEMS AND METHODS
    9.
    发明申请
    DELAY CIRCUITS AND RELATED SYSTEMS AND METHODS 审中-公开
    延迟电路及相关系统及方法

    公开(公告)号：WO2016036572A3

    公开(公告)日：2016-04-28

    申请号：PCT/US2015047153

    申请日：2015-08-27

    Applicant: QUALCOMM INC

    Inventor： AMARILIO LIOR ,  GOLUBITSKI ALEXANDER ,  HALLER HAIM HAGAY ,  KOLMAKOV FELIX ,  STHOEGER GILAD

    IPC: H03K5/13 ,  G06F1/12

    CPC classification number: H03K5/133 ,  G06F1/10 ,  G06F13/4068 ,  G06F13/4221 ,  G11C19/00 ,  H03K5/13 ,  H03K2005/0015 ,  Y02B60/1228 ,  Y02B60/1235 ,  Y02D10/14 ,  Y02D10/151

    Abstract: Delay circuits, and related systems and methods are disclosed. In one aspect, a delay circuit is provided that uses logic to delay accurately an output enable signal to reduce or avoid data hazards within a slave device. The delay circuit includes two shift register chains configured to receive an output enable in signal based on a slow clock. A first shift register chain is clocked by a positive edge of a fast clock, and provides a first strobe signal. A second shift register chain is clocked by a negative edge of the fast clock, and provides a second strobe signal. The logic uses the first and second strobe signals, and the output enable in signal, to provide a delayed output enable out signal. The delay circuit provides a highly accurate time delay for the output enable signal to reduce or avoid data hazards in an area and power efficient manner.

    Abstract translation: 公开了延迟电路及相关的系统和方法。 在一个方面，提供延迟电路，其使用逻辑来精确地延迟输出使能信号，以减少或避免从设备内的数据危害。 延迟电路包括两个移位寄存器链，其被配置为基于慢时钟接收信号中的输出使能。 第一移位寄存器链由快速时钟的上升沿提供时钟，并提供第一个选通信号。 第二移位寄存器链由快速时钟的负沿计时，并提供第二选通信号。 逻辑使用第一和第二选通信号，并且信号中的输出使能提供延迟的输出使能输出信号。 延迟电路为输出使能信号提供高度准确的时间延迟，以减少或避免一个区域的数据危害和功率有效的方式。

    CONTROL CIRCUITS FOR GENERATING OUTPUT ENABLE SIGNALS, AND RELATED SYSTEMS AND METHODS
    10.
    发明申请
    CONTROL CIRCUITS FOR GENERATING OUTPUT ENABLE SIGNALS, AND RELATED SYSTEMS AND METHODS 审中-公开
    用于产生输出使能信号的控制电路及相关系统和方法

    公开(公告)号：WO2016167933A3

    公开(公告)日：2016-11-24

    申请号：PCT/US2016023883

    申请日：2016-03-24

    Applicant: QUALCOMM INC

    Inventor： AMARILIO LIOR ,  AZIN MEYSAM ,  KHAZIN ALEXANDER ,  WANG LE

    IPC: G06F13/42

    CPC classification number: G06F1/10 ,  G06F1/06 ,  G06F13/4291

    Abstract: Control circuits for generating output enable signals are disclosed. In one aspect, a control circuit is provided that employs combinatorial logic to generate an output enable signal that meets timing constraints using a standard clock signal, a feedback clock signal based on the standard clock signal, and a single data rate (SDR) data output stream. The control circuit includes a double data rate (DDR) conversion circuit configured to generate a DDR output stream based on a received SDR output stream. The control circuit includes an output enable circuit configured to receive the standard clock signal, feedback clock signal, and DDR output stream, and to generate the output enable signal that is asserted and de-asserted according to the defined timing constraints. The control circuit is configured to generate an accurately timed output enable signal without the need for a fast clock signal in addition to the standard clock signal.

    Abstract translation: 公开了用于产生输出使能信号的控制电路。 在一个方面，提供了一种控制电路，其采用组合逻辑来产生使用标准时钟信号满足定时约束的输出使能信号，基于标准时钟信号的反馈时钟信号和单个数据速率（SDR）数据输出 流。 控制电路包括双数据速率（DDR）转换电路，配置为基于接收到的SDR输出流生成DDR输出流。 控制电路包括输出使能电路，其被配置为接收标准时钟信号，反馈时钟信号和DDR输出流，并且根据定义的时序约束生成被断言和解除断言的输出使能信号。 控制电路被配置为产生精确定时的输出使能信号，而不需要除了标准时钟信号之外的快速时钟信号。

Patent Agency Ranking