公开(公告)号：SG11201901052WA

公开(公告)日：2019-04-29

申请号：SG11201901052W

申请日：2017-09-14

Applicant: QUALCOMM INC

Inventor： XU JEFFREY ,  BADAROGLU MUSTAFA ,  YANG DA

IPC: H01L27/02 ,  H01L27/118

Abstract: Minimum track standard cell circuits for reduced area are provided. In one aspect, a minimum track standard cell circuit employs a first high aspect ratio voltage rail disposed over a first one-half track and configured to provide a first voltage (e.g., VDD) to the minimum track standard cell circuit. A second high aspect ratio voltage rail is disposed over a second one-half track substantially parallel to the first high aspect ratio voltage rail. The second high aspect ratio voltage rail is configured to provide a second voltage less than the first voltage (e.g., VSS) to the minimum track standard cell circuit. The minimum track standard cell circuit employs multiple tracks disposed between the first and second one-half tracks. The number of tracks can be limited based on particular factors. Minimizing tracks reduces area compared to conventional standard cell circuits.

公开(公告)号：AU2017216313A1

公开(公告)日：2018-07-19

申请号：AU2017216313

申请日：2017-01-06

Applicant: QUALCOMM INC

Inventor： MACHKAOUTSAN VLADIMIR ,  SONG STANLEY SEUNGCHUL ,  BADAROGLU MUSTAFA ,  ZHU JOHN JIANHONG ,  BAO JUNJING ,  XU JEFFREY JUNHAO ,  YANG DA ,  NOWAK MATTHEW MICHAEL ,  YEAP CHOH FEI

IPC: H01L29/06 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/06 ,  H01L29/423

Abstract: A device includes a substrate, a first nanowire field effect transistor (FET), and a second nanowire FET positioned between the substrate and the first nanowire FET. The device also includes a first nanowire electrically coupled to the first nanowire FET and to the second nanowire FET.

公开(公告)号：SG11201702858QA

公开(公告)日：2017-06-29

申请号：SG11201702858Q

申请日：2015-09-30

Applicant: QUALCOMM INC

Inventor： XU JEFFREY JUNHAO ,  SONG STANLEY SEUNGCHUL ,  MACHKAOUTSAN VALDIMIR ,  BADAROGLU MUSTAFA ,  BAO JUNJING ,  ZHU JOHN JIANHONG ,  YANG DA ,  YEAP CHOH FEI

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a gate stack. The semiconductor device also includes a wrap-around contact arranged around and contacting substantially all surface area of a regrown source/drain region of the semiconductor device proximate to the gate stack.

公开(公告)号：AU2017325708A1

公开(公告)日：2019-02-28

申请号：AU2017325708

申请日：2017-09-14

Applicant: QUALCOMM INC

Inventor： XU JEFFREY JUNHAO ,  BADAROGLU MUSTAFA ,  YANG DA

IPC: H01L27/02 ,  H01L27/118

Abstract: Minimum track standard cell circuits for reduced area are provided. In one aspect, a minimum track standard cell circuit employs a first high aspect ratio voltage rail disposed over a first one-half track and configured to provide a first voltage (e.g., VDD) to the minimum track standard cell circuit. A second high aspect ratio voltage rail is disposed over a second one-half track substantially parallel to the first high aspect ratio voltage rail. The second high aspect ratio voltage rail is configured to provide a second voltage less than the first voltage (e.g., VSS) to the minimum track standard cell circuit. The minimum track standard cell circuit employs multiple tracks disposed between the first and second one-half tracks. The number of tracks can be limited based on particular factors. Minimizing tracks reduces area compared to conventional standard cell circuits.

公开(公告)号：AU2017325708B2

公开(公告)日：2021-12-02

申请号：AU2017325708

申请日：2017-09-14

Applicant: QUALCOMM INC

Inventor： XU JEFFREY JUNHAO ,  BADAROGLU MUSTAFA ,  YANG DA

IPC: H01L27/02 ,  H01L27/118

Abstract: Minimum track standard cell circuits for reduced area are provided. In one aspect, a minimum track standard cell circuit employs a first high aspect ratio voltage rail disposed over a first one-half track and configured to provide a first voltage (e.g., VDD) to the minimum track standard cell circuit. A second high aspect ratio voltage rail is disposed over a second one-half track substantially parallel to the first high aspect ratio voltage rail. The second high aspect ratio voltage rail is configured to provide a second voltage less than the first voltage (e.g., VSS) to the minimum track standard cell circuit. The minimum track standard cell circuit employs multiple tracks disposed between the first and second one-half tracks. The number of tracks can be limited based on particular factors. Minimizing tracks reduces area compared to conventional standard cell circuits.

公开(公告)号：SG11201810982UA

公开(公告)日：2019-02-27

申请号：SG11201810982U

申请日：2017-06-29

Applicant: QUALCOMM INC

Inventor： XU JEFFREY ,  BADAROGLU MUSTAFA ,  YANG DA ,  CHIDAMBARAM PERIANNAN

IPC: H01L27/02 ,  G06F17/50 ,  H01L23/528 ,  H01L27/118

Abstract: Standard cell circuits employing high aspect ratio voltage rails for reduced resistance are disclosed. In one aspect, a standard cell circuit is provided that employs a first high aspect ratio voltage rail configured to receive a first supply voltage. A second high aspect ratio voltage rail is employed that is disposed substantially parallel to the first high aspect ratio voltage rail. A voltage differential between the first and second high aspect ratio voltage rails is used to power a circuit device in the standard cell circuit. The first and second high aspect ratio voltage rails each have a height-to-width ratio greater than 1.0. The height of each respective first and second high aspect ratio voltage rail is greater than each respective width. Employing the first and second high aspect ratio voltage rails allows each to have a cross-sectional area that limits the resistance and corresponding IR drop.