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    Procedimiento y aparato para codificar bits de datos en paralelo
    4.
    发明专利
    Procedimiento y aparato para codificar bits de datos en paralelo 未知

    公开(公告)号：ES2474215T3

    公开(公告)日：2014-07-08

    申请号：ES02797323

    申请日：2002-12-12

    Applicant: QUALCOMM INC

    Inventor： HURT JAMES Y ,  HOWARD MICHAEL A ,  FUCHS ROBERT J

    IPC: H03M13/27 ,  H03M13/29 ,  H03M13/00 ,  H04L1/00

    Abstract: Un procedimiento de codificación 5 de datos con un codificador (1200) de un sistema de comunicación inalámbrica, en el que el codificador es síncrono, comprendiendo el procedimiento: recibir una pluralidad de bits de información de entrada I[0]:I[3] en el codificador, en donde el procedimiento procesa la pluralidad de bits de información de entrada, I, y realiza los siguientes pasos durante un solo ciclo de reloj: - calcular los valores de estado S0[1]:S0[3], S1[1]:S1[3], S2[1]:S2[3], para el codificador, en base a la pluralidad de bits de información de entrada I[0]:I[3] y los valores de estado iniciales o almacenados S0[0] y S1[0]; y - generar un conjunto de valores codificados de salida X[0]:X[3], Y0[0]:Y0[3], Y1[0]:Y1[3] usando los valores de estado calculados S0[1]:S0[3], S1[1]:S1[3], S2[1]:S2[3], y la pluralidad de bits de información de entrada I[0]:I[3] y los valores de estado iniciales o almacenados S0[0] y S1[0] aplicando de forma recursiva: X[n] >= I[n]; Y0 [n] >= I[n] - S1[n] - S0[n]; y Y1 [n] >= I[n] - S0[n]; en las que I[n] representa un elemento n-ésimo de bits de dicha pluralidad de bits de información de entrada I[0]:I[3], X[n] representa una salida del codificador igual al n-ésimo bit de información de entrada; S0[n] y S1[n] representan elementos n-ésimos de bit de un primer y un segundo valor de estado de los valores de estado S0[0]:S03], S1[0]:S1[3], Y0[n] representa el primer elemento de bit de paridad enésimo de dicho conjunto de valores codificados de salida X[0]:X[3], Y0[0]: Y0[3], Y1[0]:Y1[3], Y1[n] representa el segundo elemento de bit de paridad enésimo de dicho conjunto de valores codificados de salida X[0]:X[3], Y0[0]:Y0[3], Y1[0]:Y1[3], - representa la operación lógica digital XOR y n representa un índice de iteración de la operación recursiva, en el que dicha etapa de cálculo de dichos valores de estado S0[1]:S0[3], S1[1]:S1[3], S2[1]:S2[3] utiliza: S0 [n + 1] >= I[n] - S1[n] - S2[n]; S1 [n + 1] >= S0[n]; y S2 [n + 1] >= S1[n], en las que S2[n] representa un elemento enésimo de bit de un tercer valor de estado S2[0]:S2[3].

    Method and apparatus for coding bits of data in parallel
    6.
    发明专利
    Method and apparatus for coding bits of data in parallel 未知

    公开(公告)号：AU2002361684A8

    公开(公告)日：2003-06-30

    申请号：AU2002361684

    申请日：2002-12-12

    Applicant: QUALCOMM INC

    Inventor： FUCHS ROBERT J ,  HOWARD MICHAEL A ,  HURT JAMES Y

    IPC: H03M13/27 ,  H03M13/00 ,  H03M13/29 ,  H04L1/00

    Abstract: A method and apparatus for encoding multiple bits in parallel wherein outputs arc generated recursively. During each clock cycle, the encoder (1500) processes multiple bits and generates outputs consistent with those generated sequentially over multiple clock cycles in a conventional convolutional encoder. In one embodiment, input data is stored in multiple memory storage units (1104 to 1106), which are then each uniquely addressed to provide data to parallel encoders.

    7.
    发明专利
    未知

    公开(公告)号：BR0214915A

    公开(公告)日：2004-12-07

    申请号：BR0214915

    申请日：2002-12-12

    Applicant: QUALCOMM INC

    Inventor： HURT JAMES Y ,  HOWARD MICHAEL A ,  FUCHS ROBERT J

    IPC: H03M13/27 ,  H03M13/00 ,  H03M13/29 ,  H04L1/00

    Abstract: A method and apparatus for encoding multiple bits in parallel wherein outputs arc generated recursively. During each clock cycle, the encoder (1500) processes multiple bits and generates outputs consistent with those generated sequentially over multiple clock cycles in a conventional convolutional encoder. In one embodiment, input data is stored in multiple memory storage units (1104 to 1106), which are then each uniquely addressed to provide data to parallel encoders.

    METHOD AND APPARATUS FOR CODING BITS OF DATA IN PARALLEL
    8.
    发明专利
    METHOD AND APPARATUS FOR CODING BITS OF DATA IN PARALLEL 未知

    公开(公告)号：AU2002361684A1

    公开(公告)日：2003-06-30

    申请号：AU2002361684

    申请日：2002-12-12

    Applicant: QUALCOMM INC

    Inventor： HURT JAMES Y ,  HOWARD MICHAEL A ,  FUCHS ROBERT J

    IPC: H03M13/27 ,  H03M13/00 ,  H03M13/29 ,  H04L1/00

    Abstract: A method and apparatus for encoding multiple bits in parallel wherein outputs arc generated recursively. During each clock cycle, the encoder (1500) processes multiple bits and generates outputs consistent with those generated sequentially over multiple clock cycles in a conventional convolutional encoder. In one embodiment, input data is stored in multiple memory storage units (1104 to 1106), which are then each uniquely addressed to provide data to parallel encoders.

    FACILITATING NOISE ESTIMATION IN WIRELESS COMMUNICATION
    10.
    发明申请
    FACILITATING NOISE ESTIMATION IN WIRELESS COMMUNICATION 审中-公开
    促进无线通信中的噪声估计

    公开(公告)号：WO2011008941A3

    公开(公告)日：2011-03-10

    申请号：PCT/US2010042120

    申请日：2010-07-15

    Applicant: QUALCOMM INC ,  ZHANG XIAOXIA ,  JETLY DARSHAN ,  XU HAO ,  FUCHS ROBERT J

    Inventor： ZHANG XIAOXIA ,  JETLY DARSHAN ,  XU HAO ,  FUCHS ROBERT J

    IPC: H04W72/04 ,  H04J13/00 ,  H04L5/00

    CPC classification number: H04W24/00 ,  H04J13/0062 ,  H04L5/0007 ,  H04L25/0206 ,  H04L25/0228 ,  H04W24/10 ,  H04W28/04 ,  H04W72/00 ,  H04W74/0833

    Abstract: Providing for noise estimation in wireless communication, and particularly for access request signals transmitted by a user equipment (UE), is described herein. By way of example, a wireless signal receiver can employ unused signal dimensions of a wireless network for noise estimation. In addition, the unused signal dimensions can be selected for time-frequency resources that are associated with a particular wireless channel, in order to obtain a noise estimate for that channel. By employing unused signal dimensions, a noise measurement is likely to include no other signal transmissions, and provide an accurate estimate of noise on that channel. According to various aspects of the subject disclosure, one or more Chu sequences employed for signal transmissions, root sequences thereof, or one or more cyclic shifts of a root sequence can be employed for the unused signal dimension.

    Abstract translation: 在此描述了无线通信中的噪声估计，并且特别地针对由用户设备（UE）发送的接入请求信号。 作为示例，无线信号接收器可以采用无线网络的未使用的信号维度来进行噪声估计。 另外，可以为与特定无线信道相关联的时频资源选择未使用的信号维度，以获得该信道的噪声估计。 通过使用未使用的信号维度，噪声测量可能不包括其他信号传输，并且提供该信道上的噪声的准确估计。 根据本发明的各个方面，用于信号传输的一个或多个Chu序列，其根序列或者根序列的一个或多个循环移位可用于未使用的信号维度。

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