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公开(公告)号：JP2010160801A
公开(公告)日：2010-07-22
申请号：JP2010023993
申请日：2010-02-05
Applicant: Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
Inventor： HENDERSON ERIC LEE , DROP MICHAEL , KAZI TAUSEEF
CPC classification number: G06F1/3296 , G06F1/3203 , Y02D10/172
Abstract: PROBLEM TO BE SOLVED: To provide optimal dynamic voltage scaling (DVS) for reducing power consumption of a microprocessor core. SOLUTION: In a method and a device for a dynamic voltage scaling (DVS) system, actual activities and critical paths inside a microprocessor core are measured using an embedded delay checker (EDC). The critical path in the microprocessor core is the basis for dynamically changing the voltage to the core. A slave ring oscillator (SRO) cell is arranged adjacent to the microprocessor core and provides redundancy to the DVS system by using together with the EDC cell. COPYRIGHT: (C)2010,JPO&INPIT
Abstract translation: 要解决的问题：提供最佳的动态电压调节（DVS），以降低微处理器内核的功耗。 解决方案：在动态电压缩放（DVS）系统的方法和设备中，使用嵌入式延迟检查器（EDC）测量微处理器内核内的实际活动和关键路径。 微处理器核心中的关键路径是动态地改变核心电压的基础。 从站环形振荡器（SRO）单元被布置在与微处理器核心相邻并且通过与EDC单元一起使用来向DVS系统提供冗余。 版权所有（C）2010，JPO＆INPIT
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公开(公告)号：JP2010160800A
公开(公告)日：2010-07-22
申请号：JP2010023992
申请日：2010-02-05
Applicant: Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
Inventor： HENDERSON ERIC LEE , DROP MICHAEL , KAZI TAUSEEF
CPC classification number: G06F1/3296 , G06F1/3203 , Y02D10/172
Abstract: PROBLEM TO BE SOLVED: To provide a method of optimizing a dynamic voltage scaling (DVS) system. SOLUTION: The dynamic voltage scaling system includes: a monitoring block for detecting the activity information and critical path delay information generated inside a microprocessor core; and a control block which reads the activity information and critical path delay information from the monitoring block, processes the activity information and critical path delay information, and adjusts the voltage supplied to the microprocessor core according to the process result of the activity information and critical path delay information. COPYRIGHT: (C)2010,JPO&INPIT
Abstract translation: 要解决的问题：提供一种优化动态电压缩放（DVS）系统的方法。 解决方案：动态电压缩放系统包括：用于检测在微处理器核心内产生的活动信息和关键路径延迟信息的监控块; 以及控制块，其从监视块读取活动信息和关键路径延迟信息，处理活动信息和关键路径延迟信息，并根据活动信息和关键路径的处理结果调整提供给微处理器核心的电压 延迟信息。 版权所有（C）2010，JPO＆INPIT
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公开(公告)号：CA2565811A1
公开(公告)日：2005-11-17
申请号：CA2565811
申请日：2005-05-05
Applicant: QUALCOMM INC
Inventor： KAZI TAUSEEF , DROP MICHAEL , HENDERSON ERIC LEE
Abstract: Methods and apparatus for implementing a Dynamic Voltage Scaling (DVS) system are presented herein. In one embodiment, an embedded delay checker (EDC) cell is used to measure the actual activity and delay of a critical path within a microprocessor core, which is the basis for dynamically altering the voltage to the core. In another embodiment, a slaved ring oscillator (SRO) cell is placed adjacent to the microprocessor core and is used along with EDC cells to provide redundancy to a DVS system.
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公开(公告)号：WO2005107428A3
公开(公告)日：2006-04-13
申请号：PCT/US2005016095
申请日：2005-05-05
Applicant: QUALCOMM INC , HENDERSON ERIC LEE , DROP MICHAEL , KAZI TAUSEEF
Inventor： HENDERSON ERIC LEE , DROP MICHAEL , KAZI TAUSEEF
CPC classification number: G06F1/3296 , G06F1/3203 , Y02D10/172
Abstract: Methods and apparatus for implementing a Dynamic Voltage Scaling (DVS) system are presented herein. In one embodiment, an embedded delay checker (EDC) cell is used to measure the actual activity and delay of a critical path within a microprocessor core, which is the basis for dynamically altering the voltage to the core. In another embodiment, a slaved ring oscillator (SRO) cell is placed adjacent to the microprocessor core and is used along with EDC cells to provide redundancy to a DVS system.
Abstract translation: 本文介绍了实现动态电压调节（DVS）系统的方法和设备。 在一个实施例中，使用嵌入式延迟检查器（EDC）单元来测量微处理器核心内的关键路径的实际活动和延迟，这是动态地改变对核心的电压的基础。 在另一个实施例中，从属环形振荡器（SRO）单元放置在与微处理器核心相邻的位置处，并与EDC单元一起使用以向DVS系统提供冗余。
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