公开(公告)号：NO20075179L

公开(公告)日：2007-12-10

申请号：NO20075179

申请日：2007-10-10

Applicant: QUALCOMM INC

Inventor： WANG MICHAEL MAO ,  JAROSINSKI TADEUSZ ,  GANAPATHY CHINNAPPA K

IPC: H04B1/16

Abstract: Disclosed are apparatus and methods for control of sleep modes in a transceiver or receiver. In particular, a transceiver is disclosed including a processor configured to determine timing information concerning sleep periods for at least a portion of components within the transceiver. The transceiver also includes a sleep control logic coupled to the processor to receive information concerning sleep periods from the processor and configured to effect shutting down of the at least a portion of the components of the transceiver during power reduction periods independent of the processor.

公开(公告)号：AU2008243160A1

公开(公告)日：2008-12-04

申请号：AU2008243160

申请日：2008-11-07

Applicant: QUALCOMM INC

Inventor： ODENWALDER JOSEPH P ,  JAROSINSKI TADEUSZ ,  IRANINEJAD MEHRABAN ,  WHEATLEY CHARLES E III ,  CARTER STEPHEN S ,  AGRE DANIEL H ,  QUICK ROY FRANKLIN JR

IPC: G09C1/00 ,  H04B1/707 ,  H04J11/00 ,  H04J13/00 ,  H04K1/00 ,  H04L9/18 ,  H04Q7/38

公开(公告)号：NO20075179A

公开(公告)日：2007-12-10

申请号：NO20075179

申请日：2007-10-10

Applicant: QUALCOMM INC

Inventor： WANG MICHAEL MAO ,  JAROSINSKI TADEUSZ ,  GANAPATHY CHINNAPPA K

IPC: H04B1/16

CPC classification number: H04W52/0225 ,  H04B1/1615 ,  H04W52/0293 ,  Y02D70/1222 ,  Y02D70/1242 ,  Y02D70/164 ,  Y02D70/40

Abstract: Disclosed are apparatus and methods for control of sleep modes in a transceiver or receiver. In particular, a transceiver is disclosed including a processor configured to determine timing information concerning sleep periods for at least a portion of components within the transceiver. The transceiver also includes a sleep control logic coupled to the processor to receive information concerning sleep periods from the processor and configured to effect shutting down of the at least a portion of the components of the transceiver during power reduction periods independent of the processor.

公开(公告)号：ES2753373T3

公开(公告)日：2020-04-08

申请号：ES14737434

申请日：2014-06-13

Applicant: QUALCOMM INC

Inventor： JOHN ARCHIBALD FITZGERALD ,  RABII KHOSRO MOHAMMAD ,  DAMECHARLA HIMA BINDU ,  JAROSINSKI TADEUSZ ,  SWAMINATHAN ASHWIN

IPC: G06F1/3215 ,  G06F1/3234 ,  G06K9/00 ,  H04N5/232 ,  H04N7/18

Abstract: Un procedimiento que comprende: generar, en un circuito de detección de cambio (414, 514, 614, 814) incluido en una primera ruta de procesamiento (408, 508, 608, 808), una señal de control en base a una cantidad de cambio entre los primeros datos del sensor (112) y los segundos datos del sensor (114) que satisface un umbral, los primeros datos del sensor (112) correspondientes a un primer conjunto de valores de píxel asociados a una primera imagen (102) captada por un primer sensor (402, 502, 602, 842) y los segundos datos del sensor (114) correspondientes a un segundo conjunto de valores de píxel asociados a una segunda imagen (104) captada por el primer sensor (402, 502, 602, 842); el procedimiento caracterizado por proporcionar los segundos datos del sensor (114) a una segunda ruta de procesamiento (410, 510, 610, 810) para el procesamiento específico de la aplicación de visión informática en base a la señal de control (416, 516, 844), la segunda ruta de procesamiento (410, 510, 610, 810) diferente de la primera ruta de procesamiento (408, 508, 606, 808), en el que la potencia informática para la primera ruta de procesamiento (408, 508, 608, 808) es menor que la potencia informática para la segunda ruta de procesamiento (410, 510, 610, 810).

公开(公告)号：SG160383A1

公开(公告)日：2010-04-29

申请号：SG2010016194

申请日：2006-03-13

Applicant: QUALCOMM INC

Inventor： JAROSINSKI TADEUSZ ,  GANAPATHY CHINNAPPA K ,  WANG MICHAEL MAO

Abstract: Disclosed are apparatus and methods for control of sleep modes in a transceiver or receiver. In particular, a transceiver is disclosed including a processor configured to determine timing information concerning sleep periods for at least a portion of components within the transceiver. The transceiver also includes a sleep control logic coupled to the processor to receive information concerning sleep periods from the processor and configured to effect shutting down of the at least a portion of the components of the transceiver during power reduction periods independent of the processor.

公开(公告)号：MX2007011095A

公开(公告)日：2007-11-22

申请号：MX2007011095

申请日：2006-03-13

Applicant: QUALCOMM INC

Inventor： GANAPATHY CHINNAPPA K ,  WANG MICHAEL MAO ,  JAROSINSKI TADEUSZ

IPC: H04B1/16 ,  H04M1/73

Abstract: Se describen aparatos y metodos para control de modos de espera en un transceptor o receptor; en particular, se describe un transceptor que incluye un procesador configurado para determinar informacion de temporizacion relacionada con periodos de espera por lo menos para una porcion de componentes dentro del transceptor; el transceptor tambien incluye logica de control de espera acoplada al procesador para recibir informacion relacionada con periodos de espera del procesador y configurada para efectuar el apagado por lo menos de una porcion de los componentes del transceptor durante periodos de reduccion de potencia independiente del procesador.

公开(公告)号：CA2600490A1

公开(公告)日：2006-09-21

申请号：CA2600490

申请日：2006-03-13

Applicant: QUALCOMM INC

Inventor： JAROSINSKI TADEUSZ ,  GANAPATHY CHINNAPPA K ,  WANG MICHAEL MAO

IPC: H04B1/16 ,  H04M1/73

Abstract: Disclosed are apparatus and methods for control of sleep modes in a transceiver or receiver. In particular, a transceiver is disclosed including a processor configured to determine timing information concerning sleep periods for at least a portion of components within the transceiver. The transceiver also includes a sleep control logic coupled to the processor to receive information concerning sleep periods from the processor and configured to effect shutting down of the at least a portion of the components of the transceiver during power reduction periods independent of the processor.

公开(公告)号：AU2006222969A1

公开(公告)日：2006-09-21

申请号：AU2006222969

申请日：2006-03-13

Applicant: QUALCOMM INC

Inventor： WANG MICHAEL MAO ,  JAROSINSKI TADEUSZ ,  GANAPATHY CHINNAPPA K

IPC: H04B1/16 ,  H04M1/73

Abstract: Disclosed are apparatus and methods for control of sleep modes in a transceiver or receiver. In particular, a transceiver is disclosed including a processor configured to determine timing information concerning sleep periods for at least a portion of components within the transceiver. The transceiver also includes a sleep control logic coupled to the processor to receive information concerning sleep periods from the processor and configured to effect shutting down of the at least a portion of the components of the transceiver during power reduction periods independent of the processor.

公开(公告)号：HUE045984T2

公开(公告)日：2020-01-28

申请号：HUE14737434

申请日：2014-06-13

Applicant: QUALCOMM INC

Inventor： JOHN ARCHIBALD FITZGERALD ,  RABII KHOSRO MOHAMMAD ,  DAMECHARLA HIMA BINDU ,  JAROSINSKI TADEUSZ ,  SWAMINATHAN ASHWIN

IPC: G06K9/00 ,  H04N7/18

公开(公告)号：BRPI0608226A2

公开(公告)日：2009-11-24

申请号：BRPI0608226

申请日：2006-03-13

Applicant: QUALCOMM INC

Inventor： JAROSINSKI TADEUSZ ,  WANG MICHAEL MAO ,  GANAPATHY CHINNAPPA K

IPC: H04B1/16 ,  H04M1/73

Abstract: Disclosed are apparatus and methods for control of sleep modes in a transceiver or receiver. In particular, a transceiver is disclosed including a processor configured to determine timing information concerning sleep periods for at least a portion of components within the transceiver. The transceiver also includes a sleep control logic coupled to the processor to receive information concerning sleep periods from the processor and configured to effect shutting down of the at least a portion of the components of the transceiver during power reduction periods independent of the processor.