Configurable mixer
    1.
    发明专利

    公开(公告)号:AU2017332549B2

    公开(公告)日:2022-06-09

    申请号:AU2017332549

    申请日:2017-08-14

    Applicant: QUALCOMM INC

    Abstract: A method and apparatus are disclosed for a configurable mixer capable of operating in a linear, a legacy, and a low-power mode. In the linear mode, the configurable mixer is configured to operate as a double-balanced mixer to multiply a first differential signal by a second differential signal. In the legacy mode, the configurable mixer is configured to as a double-balanced mixer to multiply a differential signal by a single-ended signal. In the low-power mode, the configurable mixer is configured to operate as a single-balanced mixer to multiply a differential signal by a single-ended signal. The operating mode of the configurable mixer may be based, at least in part, on a mode control signal. In some embodiments, the configurable mixer may be included in an analog front end of a wireless communication device.

    Receptor de señales simultáneas con asignación de frecuencia intercalada

    公开(公告)号:ES2733275T3

    公开(公告)日:2019-11-28

    申请号:ES14711423

    申请日:2014-03-05

    Applicant: QUALCOMM INC

    Abstract: Un procedimiento para procesamiento de señales, que comprende: convertir de forma descendente al menos una primera señal de RF en una primera ruta en una primera banda de frecuencias para proporcionar una primera señal de IF que comprende una primera señal de componente I y una primera señal de componente Q; convertir de forma descendente al menos una segunda señal de RF en la segunda ruta en una segunda banda de frecuencias para proporcionar una segunda señal de IF que comprende una segunda señal de componente I y una segunda señal de componente Q, en el que la primera señal de IF y la segunda señal de IF están intercaladas en el dominio de frecuencia, siendo la primera banda de frecuencias diferente de la segunda banda de frecuencias; combinar la primera señal de componente I y la primera señal de componente Q utilizando un primer filtro polifásico para proporcionar una tercera señal de IF; combinar la segunda señal de componente I y la segunda señal de componente Q utilizando un segundo filtro polifásico para proporcionar una cuarta señal de IF; y combinar al menos parte de la tercera señal de IF y la cuarta señal de IF para proporcionar una señal combinada en una ruta de señal de salida para la recepción mediante un circuito de procesamiento digital.

    Configurable mixer
    3.
    发明专利

    公开(公告)号:AU2017332549A1

    公开(公告)日:2019-03-07

    申请号:AU2017332549

    申请日:2017-08-14

    Applicant: QUALCOMM INC

    Abstract: A method and apparatus are disclosed for a configurable mixer capable of operating in a linear, a legacy, and a low-power mode. In the linear mode, the configurable mixer is configured to operate as a double-balanced mixer to multiply a first differential signal by a second differential signal. In the legacy mode, the configurable mixer is configured to as a double-balanced mixer to multiply a differential signal by a single-ended signal. In the low-power mode, the configurable mixer is configured to operate as a single-balanced mixer to multiply a differential signal by a single-ended signal. The operating mode of the configurable mixer may be based, at least in part, on a mode control signal. In some embodiments, the configurable mixer may be included in an analog front end of a wireless communication device.

    SINGLE DIFFERENTIAL TRANSFORMER CORE

    公开(公告)号:IN2598CHN2014A

    公开(公告)日:2015-08-14

    申请号:IN2598CHN2014

    申请日:2014-04-04

    Applicant: QUALCOMM INC

    Abstract: An integrated circuit is disclosed. The integrated circuit includes a primary coil. The integrated circuit also includes a first secondary coil that acts as a first transformer with the primary coil. The integrated circuit further includes a second secondary coil that acts as a second transformer with the primary coil. The primary coil the first secondary coil and the second secondary coil have a layout on the integrated circuit to minimize coupling between the first secondary coil and the second secondary coil.

    OSCILLATOR SIGNAL GENERATION WITH SPUR MITIGATION IN A WIRELESS COMMUNICATION DEVICE

    公开(公告)号:CA2698268A1

    公开(公告)日:2009-03-19

    申请号:CA2698268

    申请日:2008-09-11

    Applicant: QUALCOMM INC

    Abstract: Techniques for generating oscillator signals in a wireless communication device are described. A phase-locked loop (PLL) may be used to generate an oscillator signal for a selected frequency channel. Different PLL settings may be used for the blocks in the PLL for different frequency channels. The different PLL settings may be for different PLL loop bandwidths, different amounts of charge pump current, different frequency equations associated with different sets of high and low divider ratios, different frequency division schemes associated with different prescaler ratios and/or different integer divider ratios, high side or low side injection for a super-heterodyne receiver or transmitter, and/or different supply voltages for one or more circuit blocks such as an oscillator. A suitable set of PLL settings may be selected for each frequency channel such that adverse impact due to spurs can be mitigated.

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