公开(公告)号：CA2983800A1

公开(公告)日：2016-12-08

申请号：CA2983800

申请日：2016-04-27

Applicant: QUALCOMM INC

Inventor： GADELRAB SERAG MONIER ,  KOOB CHRISTOPHER EDWARD ,  BOOTH SIMON ,  BALATSOS ARIS ,  KUAN JOHNNY JONE WAI ,  RAMKUMAR MYIL ,  PABLA BHUPINDER SINGH ,  SWEENEY SEAN DAVID ,  PATSILARAS GEORGE

IPC: G06F9/46 ,  G06F9/48 ,  G06F11/07

Abstract: Systems and methods relate to managing shared resources in a multithreaded processor comprising two or more processing threads. Danger levels for the two or more threads are determined, wherein the danger level of a thread is based on a potential failure of the thread to meet a deadline due to unavailability of a shared resource. Priority levels associated with the two or more threads are also determined, wherein the priority level is higher for a thread whose failure to meet a deadline is unacceptable and the priority level is lower for a thread whose failure to meet a deadline is acceptable. The two or more threads are scheduled based at least on the determined danger levels for the two or more threads and priority levels associated with the two or more threads.

公开(公告)号：EP3183659B1

公开(公告)日：2018-01-10

申请号：EP15747700

申请日：2015-07-24

Applicant: QUALCOMM INC

Inventor： PATSILARAS GEORGE ,  IRANLI ALI ,  TURNER ANDREW EDMUND ,  RYCHLIK BOHUSLAV

IPC: G06F12/08 ,  G06F12/0886 ,  G06F12/0893

CPC classification number: G06F12/0893 ,  G06F12/0886 ,  G06F2212/1028 ,  G06F2212/1044 ,  G06F2212/401 ,  Y02B60/1225 ,  Y02D10/13

Abstract: Aspects include computing devices, systems, and methods for implementing a cache memory access requests for data smaller than a cache line and eliminating overfetching from a main memory by combining the data with padding data of a size of a difference between a size of a cache line and the data. A processor may determine whether the data, uncompressed or compressed, is smaller than a cache line using a size of the data or a compression ratio of the data. The processor may generate the padding data using constant data values or a pattern of data values. The processor may send a write cache memory access request for the combined data to a cache memory controller, which may write the combined data to a cache memory. The cache memory controller may send a write memory access request to a memory controller, which may write the combined data to a memory.

公开(公告)号：EP3178005B1

公开(公告)日：2018-01-10

申请号：EP15742447

申请日：2015-07-09

Applicant: QUALCOMM INC

Inventor： TURNER ANDREW EDMUND ,  PATSILARAS GEORGE ,  RYCHLIK BOHUSLAV

IPC: G06F12/0886 ,  G06F12/0802

CPC classification number: G06F12/0875 ,  G06F12/0802 ,  G06F12/0886 ,  G06F2212/1021 ,  G06F2212/401 ,  G06F2212/45 ,  G06F2212/608

Abstract: Methods, devices, and non-transitory process-readable storage media for compacting data within cache lines of a cache. An aspect method may include identifying, by a processor of the computing device, a base address (e.g., a physical or virtual cache address) for a first data segment, identifying a data size (e.g., based on a compression ratio) for the first data segment, obtaining a base offset based on the identified data size and the base address of the first data segment, and calculating an offset address by offsetting the base address with the obtained base offset, wherein the calculated offset address is associated with a second data segment. In some aspects, the method may include identifying a parity value for the first data segment based on the base address and obtaining the base offset by performing a lookup on a stored table using the identified data size and identified parity value.