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公开(公告)号：HK1063888A1
公开(公告)日：2005-01-14
申请号：HK04106568
申请日：2004-09-01
Applicant: QUALCOMM INC
Inventor： BAZARJANI SEYFOLLAH , WANG SEAN , PELUSO VINCENZO
IPC: H03M20060101 , H03M3/02
Abstract: A control mechanism that can be used to control a SIGMADELTA ADC to provide the required level of performance while reducing power consumption. The SIGMADELTA ADC is designed with multiple stages (i.e., loops or sections), and provides improved performance (e.g., higher dynamic range) as more stages are enabled. The control mechanism selectively enables a sufficient number of stages to provide the required performance and disables remaining stages to conserve power. The control mechanism achieves this by measuring one or more characteristics (e.g., signal level) of the ADC input signal through a SIGMADELTA ADC that is similar to the SIGMADELTA ADC on the signal path, comparing the measured characteristic(s) to particular threshold level(s), and controlling the stages such that the desired objectives are achieved. In one implementation, the control circuit includes one or more detector stages, a conditioning circuit, and a signal processor. The detector stage(s) receive the input signal and provide a detected signal. The conditioning circuit receives the detected signal and provides conditioned samples. The signal processor receives the conditioned samples and provides a control signal that selectively disables zero or more SIGMADELTA stages in the SIGMADELTA ADC.
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公开(公告)号：AU2718702A
公开(公告)日：2002-05-15
申请号：AU2718702
申请日：2001-10-31
Applicant: QUALCOMM INC
Inventor： BAZARJANI SEYFOLLAH , WANG SEAN , PELUSO VINCENZO
IPC: H03M3/02
Abstract: A control mechanism that can be used to control a SIGMADELTA ADC to provide the required level of performance while reducing power consumption. The SIGMADELTA ADC is designed with multiple stages (i.e., loops or sections), and provides improved performance (e.g., higher dynamic range) as more stages are enabled. The control mechanism selectively enables a sufficient number of stages to provide the required performance and disables remaining stages to conserve power. The control mechanism achieves this by measuring one or more characteristics (e.g., signal level) of the ADC input signal through a SIGMADELTA ADC that is similar to the SIGMADELTA ADC on the signal path, comparing the measured characteristic(s) to particular threshold level(s), and controlling the stages such that the desired objectives are achieved. In one implementation, the control circuit includes one or more detector stages, a conditioning circuit, and a signal processor. The detector stage(s) receive the input signal and provide a detected signal. The conditioning circuit receives the detected signal and provides conditioned samples. The signal processor receives the conditioned samples and provides a control signal that selectively disables zero or more SIGMADELTA stages in the SIGMADELTA ADC.
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公开(公告)号：CA2427423C
公开(公告)日：2009-09-29
申请号：CA2427423
申请日：2001-10-31
Applicant: QUALCOMM INC
Inventor： WANG SEAN , PELUSO VINCENZO , BAZARJANI SEYFOLLAH
IPC: H03M3/02
Abstract: A control mechanism that can be used to control a .SIGMA..DELTA. to provide the required level of performance while reducing power consumption. The .SIGMA..DELTA. ADC is designe dwith multiple stage (i.e., loops or sections) , and provides improved performance (e.g., higher dynamic range) as more stage s are enabled. The control mechanism selectively enables a sufficient number o f stages to provide the required performance and disables remaining stages to conserve power. The control mechanism achieves this by measuring one or more characteristics (e.g., signal level) of the ADC input signal through a .SIGMA..DELTA. ADC that is similar to the .SIGMA..DELTA. ADC on the signal path, comparing the measured characteristic(s) to particular threshold level(s), and controlling the stages such that the desired objectives are achieved. In one implementation, the control circuit includes one or more detector stages, a conditioning circuit, and a signal processor. The detecto r stage(s) receive the input signal and provide a detected signal. The conditioning circuit receives the detected signal and provides conditined samples. The signal processor receives the conditioned samples and provides a control signal that selectively disables zero or more .SIGMA..DELTA. stages in the .SIGMA..DELTA. ADC.
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公开(公告)号：CA2427423A1
公开(公告)日：2002-05-10
申请号：CA2427423
申请日：2001-10-31
Applicant: QUALCOMM INC
Inventor： BAZARJANI SEYFOLLAH , PELUSO VINCENZO , WANG SEAN
IPC: H03M3/02
Abstract: A control mechanism that can be used to control a .SIGMA..DELTA. to provide the required level of performance while reducing power consumption. The .SIGMA..DELTA. ADC is designe dwith multiple stage (i.e., loops or sections), and provides improved performance (e.g., higher dynamic range) as more stages are enabled. The control mechanism selectively enables a sufficient number of stages to provide the required performance and disables remaining stages to conserve power. The control mechanism achieves this by measuring one or more characteristics (e.g., signal level) of the ADC input signal through a .SIGMA..DELTA. ADC that is similar to the .SIGMA..DELTA. ADC on the signal path, comparing the measured characteristic(s) to particular threshold level(s), and controlling the stages such that the desired objectives are achieved. In one implementation, the control circuit includes one or more detector stages, a conditioning circuit, and a signal processor. The detector stage(s) receive the input signal and provide a detected signal. The conditioning circuit receives the detected signal and provides conditined samples. The signal processor receives the conditioned samples and provides a control signal that selectively disables zero or more .SIGMA..DELTA. stages in the .SIGMA..DELTA. ADC.
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公开(公告)号：DE60131027T2
公开(公告)日：2008-07-17
申请号：DE60131027
申请日：2001-10-31
Applicant: QUALCOMM INC
Inventor： BAZARJANI SEYFOLLAH , WANG SEAN , PELUSO VINCENZO
IPC: H03M3/02
Abstract: A control mechanism that can be used to control a SIGMADELTA ADC to provide the required level of performance while reducing power consumption. The SIGMADELTA ADC is designed with multiple stages (i.e., loops or sections), and provides improved performance (e.g., higher dynamic range) as more stages are enabled. The control mechanism selectively enables a sufficient number of stages to provide the required performance and disables remaining stages to conserve power. The control mechanism achieves this by measuring one or more characteristics (e.g., signal level) of the ADC input signal through a SIGMADELTA ADC that is similar to the SIGMADELTA ADC on the signal path, comparing the measured characteristic(s) to particular threshold level(s), and controlling the stages such that the desired objectives are achieved. In one implementation, the control circuit includes one or more detector stages, a conditioning circuit, and a signal processor. The detector stage(s) receive the input signal and provide a detected signal. The conditioning circuit receives the detected signal and provides conditioned samples. The signal processor receives the conditioned samples and provides a control signal that selectively disables zero or more SIGMADELTA stages in the SIGMADELTA ADC.
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Patent Agency Ranking
公开(公告)号：AT376283T
公开(公告)日：2007-11-15
申请号：AT01993064
申请日：2001-10-31
Applicant: QUALCOMM INC
Inventor： BAZARJANI SEYFOLLAH , WANG SEAN , PELUSO VINCENZO
IPC: H03M3/02
Abstract: A control mechanism that can be used to control a SIGMADELTA ADC to provide the required level of performance while reducing power consumption. The SIGMADELTA ADC is designed with multiple stages (i.e., loops or sections), and provides improved performance (e.g., higher dynamic range) as more stages are enabled. The control mechanism selectively enables a sufficient number of stages to provide the required performance and disables remaining stages to conserve power. The control mechanism achieves this by measuring one or more characteristics (e.g., signal level) of the ADC input signal through a SIGMADELTA ADC that is similar to the SIGMADELTA ADC on the signal path, comparing the measured characteristic(s) to particular threshold level(s), and controlling the stages such that the desired objectives are achieved. In one implementation, the control circuit includes one or more detector stages, a conditioning circuit, and a signal processor. The detector stage(s) receive the input signal and provide a detected signal. The conditioning circuit receives the detected signal and provides conditioned samples. The signal processor receives the conditioned samples and provides a control signal that selectively disables zero or more SIGMADELTA stages in the SIGMADELTA ADC.
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公开(公告)号：DE60131027D1
公开(公告)日：2007-11-29
申请号：DE60131027
申请日：2001-10-31
Applicant: QUALCOMM INC
Inventor： BAZARJANI SEYFOLLAH , WANG SEAN , PELUSO VINCENZO
IPC: H03M3/02
Abstract: A control mechanism that can be used to control a SIGMADELTA ADC to provide the required level of performance while reducing power consumption. The SIGMADELTA ADC is designed with multiple stages (i.e., loops or sections), and provides improved performance (e.g., higher dynamic range) as more stages are enabled. The control mechanism selectively enables a sufficient number of stages to provide the required performance and disables remaining stages to conserve power. The control mechanism achieves this by measuring one or more characteristics (e.g., signal level) of the ADC input signal through a SIGMADELTA ADC that is similar to the SIGMADELTA ADC on the signal path, comparing the measured characteristic(s) to particular threshold level(s), and controlling the stages such that the desired objectives are achieved. In one implementation, the control circuit includes one or more detector stages, a conditioning circuit, and a signal processor. The detector stage(s) receive the input signal and provide a detected signal. The conditioning circuit receives the detected signal and provides conditioned samples. The signal processor receives the conditioned samples and provides a control signal that selectively disables zero or more SIGMADELTA stages in the SIGMADELTA ADC.
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公开(公告)号：BR0115060A
公开(公告)日：2005-10-18
申请号：BR0115060
申请日：2001-10-31
Applicant: QUALCOMM INC
Inventor： BAZARJANI SEYFOLLAH , WANG SEAN , PELUSO VINCENZO
IPC: H03M3/02
Abstract: A control mechanism that can be used to control a SIGMADELTA ADC to provide the required level of performance while reducing power consumption. The SIGMADELTA ADC is designed with multiple stages (i.e., loops or sections), and provides improved performance (e.g., higher dynamic range) as more stages are enabled. The control mechanism selectively enables a sufficient number of stages to provide the required performance and disables remaining stages to conserve power. The control mechanism achieves this by measuring one or more characteristics (e.g., signal level) of the ADC input signal through a SIGMADELTA ADC that is similar to the SIGMADELTA ADC on the signal path, comparing the measured characteristic(s) to particular threshold level(s), and controlling the stages such that the desired objectives are achieved. In one implementation, the control circuit includes one or more detector stages, a conditioning circuit, and a signal processor. The detector stage(s) receive the input signal and provide a detected signal. The conditioning circuit receives the detected signal and provides conditioned samples. The signal processor receives the conditioned samples and provides a control signal that selectively disables zero or more SIGMADELTA stages in the SIGMADELTA ADC.
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公开(公告)号：WO2016122977A3
公开(公告)日：2016-09-22
申请号：PCT/US2016014472
申请日：2016-01-22
Applicant: QUALCOMM INC
Inventor： PELUSO VINCENZO , LIU BING
IPC: G05F1/575
Abstract: The present disclosure includes circuits and methods for generating bleeding currents. In one embodiment, a pass transistor of a voltage regulator receives a voltage from a feedback circuit. A negative resistance circuit is coupled to a node to produce a bleeding current that turns on when needed and is otherwise off to save power. In one embodiment, the negative resistance circuit includes stacked current mirrors and a resistor. In another embodiment, the resistor has a first terminal that receives the voltage from the feedback circuit and a second terminal is coupled to a constant reference voltage that tracks the input voltage.
Abstract translation: 本公开包括用于产生放电电流的电路和方法。 在一个实施例中，电压调节器的传输晶体管从反馈电路接收电压。 负电阻电路耦合到节点以产生放电电流，该电流在需要时开启，否则关闭以节省电力。 在一个实施例中，负阻电路包括堆叠的电流镜和电阻器。 在另一个实施例中，电阻器具有第一端子和第二端子，第一端子接收来自反馈电路的电压，第二端子连接至跟踪输入电压的恒定参考电压。
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10.发明申请
公开(公告)号：WO0237686A3
公开(公告)日：2004-02-19
申请号：PCT/US0146188
申请日：2001-10-31
Applicant: QUALCOMM INC
Inventor： BAZARJANI SEYFOLLAH , WANG SEAN , PELUSO VINCENZO
IPC: H03M3/02
Abstract: A control mechanism that can be used to control a SIGMA DELTA to provide the required level of performance while reducing power consumption. The SIGMA DELTA ADC is designe dwith multiple stage (i.e., loops or sections), and provides improved performance (e.g., higher dynamic range) as more stages are enabled. The control mechanism selectively enables a sufficient number of stages to provide the required performance and disables remaining stages to conserve power. The control mechanism achieves this by measuring one or more characteristics (e.g., signal level) of the ADC input signal through a SIGMA DELTA ADC that is similar to the SIGMA DELTA ADC on the signal path, comparing the measured characteristic(s) to particular threshold level(s), and controlling the stages such that the desired objectives are achieved. In one implementation, the control circuit includes one or more detector stages, a conditioning circuit, and a signal processor. The detector stage(s) receive the input signal and provide a detected signal. The conditioning circuit receives the detected signal and provides conditined samples. The signal processor receives the conditioned samples and provides a control signal that selectively disables zero or more SIGMA DELTA stages in the SIGMA DELTA ADC.
Abstract translation: 一种可用于控制SIGMA DELTA以提供所需性能水平同时降低功耗的控制机制。 SIGMA DELTA ADC设计为多级（即，环路或部分），并且随着更多级的启用，提供改进的性能（例如，更高的动态范围）。 控制机构选择性地实现足够数量的级以提供所需性能并且禁用剩余级以节省功率。 控制机制通过测量信号路径上类似于SIGMA DELTA ADC的SIGMA DELTA ADC的ADC输入信号的一个或多个特性（例如，信号电平）来实现这一点，将测量特性与特定阈值进行比较 级别，并控制阶段以达到所需目标。 在一个实现中，控制电路包括一个或多个检测器级，调理电路和信号处理器。 检测器级接收输入信号并提供检测信号。 调理电路接收检测到的信号并提供条件样本。 信号处理器接收经调节的样本并提供选择性地禁用SIGMA DELTA ADC中的零个或更多个SIGMA DELTA级的控制信号。
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