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    Candidate system search and soft handoff between frequencies in multi-carrier mobile communication system
    2.
    发明专利
    Candidate system search and soft handoff between frequencies in multi-carrier mobile communication system 有权
    多载波移动通信系统中的频率之间的候选系统搜索和软交换

    公开(公告)号：JP2011082996A

    公开(公告)日：2011-04-21

    申请号：JP2010237338

    申请日：2010-10-22

    Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

    Inventor： CHEN TAO ,  BAZARJANI SEYFOLLAH ,  TIEDEMANN EDWARD G JR

    IPC: H04B1/7073 ,  H04J1/02 ,  H04B1/16 ,  H04Q7/22

    CPC classification number: H04B7/0491 ,  H04B7/022

    Abstract: PROBLEM TO BE SOLVED: To provide a mobile communication system in which a mobile station can receive and decode a signal transmitted in one or more frequencies.
    SOLUTION: The mobile communication system includes a mobile station having a transmitter 210 to transmit an output signal from the mobile station 200 and a receiver 220 to receive an input signal. The receiver is connected to the transmitter and has N-sets of sub-receivers 225, where N is an integer larger than 1, and each of N-sets of sub-receivers is tuned to a desired frequency, independently. The wireless communication system is composed of (1) a plurality of base stations in which each base station transmits a signal in at least one frequency of a plurality of frequencies, and a plurality of mobile stations (2) in which at least one of a plurality of mobile stations includes (a) a transmitter to transmit a signal to at least one of a plurality of base stations and a receiver connected to a transmitter to receive a signal from at least one of a plurality of base stations, wherein the receiver has N-sets of sub-receivers, where N is an integer of 1 or more, and each of N-sets of sub-receivers is tuned to a desired frequency, independently.
    COPYRIGHT: (C)2011,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种移动通信系统，其中移动站可以接收和解码以一个或多个频率发送的信号。 解决方案：移动通信系统包括具有发射机210的移动站，发射机210从移动台200发送输出信号，接收机220接收输入信号。 接收机连接到发射机，并且具有N组子接收机225，其中N是大于1的整数，并且N组子接收机中的每一个独立地被调谐到期望的频率。 无线通信系统包括：（1）多个基站，每个基站以多个频率的至少一个频率发送信号;以及多个移动台（2），其中，至少一个 多个移动站包括：（a）向多个基站中的至少一个发送信号的发射机和连接到发射机的接收机，以从多个基站中的至少一个基站接收信号，其中接收机具有 N组子接收机，其中N是1或更大的整数，并且N组子接收机中的每一个独立地被调谐到期望的频率。 版权所有（C）2011，JPO＆INPIT

    Circuit and method for adjusting circuit tolerance
    3.
    发明专利
    Circuit and method for adjusting circuit tolerance 审中-公开
    调整电路容差的电路和方法

    公开(公告)号：JP2011061822A

    公开(公告)日：2011-03-24

    申请号：JP2010232566

    申请日：2010-10-15

    Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

    Inventor： BAZARJANI SEYFOLLAH

    IPC: H03H11/04 ,  H03H7/12 ,  H03H11/12

    CPC classification number: H03H7/12 ,  H03H11/1291

    Abstract: PROBLEM TO BE SOLVED: To provide a frequency response adjuster for a frequency responsive circuit, and a method for tuning a frequency response of a circuit.
    SOLUTION: The adjuster includes: a time constant sensor which measures and outputs a charging state of the frequency responsive circuit as a first voltage; a converter which samples the first voltage and outputs a second voltage resulting from a conversion of the first voltage; an array of trimming components; and a selector which utilizes the second voltage to select at least one trimming component from the array of trimming components. The method includes the steps of: sensing a time constant of the circuit; outputting the sensing as the first voltage; sampling the first voltage over a fixed interval; converting the sampled first voltage to the second voltage; and selecting at least one trimming component from the array of trimming components utilizing the second voltage.
    COPYRIGHT: (C)2011,JPO&INPIT

    Abstract translation: 要解决的问题：提供用于频率响应电路的频率响应调节器，以及用于调谐电路的频率响应的方法。 调节器包括：时间常数传感器，其测量并输出频率响应电路的充电状态作为第一电压; 转换器，其对第一电压进行采样并输出由第一电压的转换产生的第二电压; 一系列修剪组件; 以及选择器，其利用所述第二电压从所述修整组件阵列中选择至少一个修整组件。 该方法包括以下步骤：感测电路的时间常数; 输出感测作为第一电压; 在固定间隔内对第一电压进行采样; 将采样的第一电压转换为第二电压; 以及利用所述第二电压从所述修整部件阵列中选择至少一个修整部件。 版权所有（C）2011，JPO＆INPIT

    6.
    发明专利
    未知

    公开(公告)号：DE60236147D1

    公开(公告)日：2010-06-10

    申请号：DE60236147

    申请日：2002-01-30

    Applicant: QUALCOMM INC

    Inventor： BAZARJANI SEYFOLLAH

    IPC: H03M3/02 ,  H03H17/06

    Abstract: A multi-stage circuit that includes a number of stages, with at least one stage being of a first type and at least one stage being of a second type. Each stage receives either a circuit input signal or an output signal from a preceding stage, processes (e.g., filters) the received signal, and provides a respective output signal. Each first type (or second type) stage operates based on one or more clock signals having a frequency of fS (or fS/N), where fS is the sampling frequency and N is an integer greater than one. Each first type stage may be implemented with a correlated double-sampling circuit, an auto-zeroing circuit, or a chopper stabilization circuit. Each second type stage may be implemented with a multi-sampling (i.e., double-sampling or higher order sampling) circuit. The multi-stage circuit may be designed to implement a lowpass filter, a DELTASIGMA ADC, or some other circuit.

    Method and apparatus for controlling stages of a multi-stage circuit
    7.
    发明专利
    Method and apparatus for controlling stages of a multi-stage circuit 未知

    公开(公告)号：HK1063888A1

    公开(公告)日：2005-01-14

    申请号：HK04106568

    申请日：2004-09-01

    Applicant: QUALCOMM INC

    Inventor： BAZARJANI SEYFOLLAH ,  WANG SEAN ,  PELUSO VINCENZO

    IPC: H03M20060101 ,  H03M3/02

    Abstract: A control mechanism that can be used to control a SIGMADELTA ADC to provide the required level of performance while reducing power consumption. The SIGMADELTA ADC is designed with multiple stages (i.e., loops or sections), and provides improved performance (e.g., higher dynamic range) as more stages are enabled. The control mechanism selectively enables a sufficient number of stages to provide the required performance and disables remaining stages to conserve power. The control mechanism achieves this by measuring one or more characteristics (e.g., signal level) of the ADC input signal through a SIGMADELTA ADC that is similar to the SIGMADELTA ADC on the signal path, comparing the measured characteristic(s) to particular threshold level(s), and controlling the stages such that the desired objectives are achieved. In one implementation, the control circuit includes one or more detector stages, a conditioning circuit, and a signal processor. The detector stage(s) receive the input signal and provide a detected signal. The conditioning circuit receives the detected signal and provides conditioned samples. The signal processor receives the conditioned samples and provides a control signal that selectively disables zero or more SIGMADELTA stages in the SIGMADELTA ADC.

    HYBRID MULTI-STAGE CIRCUIT UTILIZING DIFFERENT TYPES OF SAMPLING CIRCUIT
    8.
    发明专利
    HYBRID MULTI-STAGE CIRCUIT UTILIZING DIFFERENT TYPES OF SAMPLING CIRCUIT 未知

    公开(公告)号：HK1062088A1

    公开(公告)日：2004-10-15

    申请号：HK04105031

    申请日：2004-07-09

    Applicant: QUALCOMM INC

    Inventor： BAZARJANI SEYFOLLAH

    IPC: H03H20100101 ,  H03M20100101 ,  H03M3/02

    Abstract: A multi-stage circuit that includes a number of stages, with at least one stage being of a first type and at least one stage being of a second type. Each stage receives either a circuit input signal or an output signal from a preceding stage, processes (e.g., filters) the received signal, and provides a respective output signal. Each first type (or second type) stage operates based on one or more clock signals having a frequency of fS (or fS/N), where fS is the sampling frequency and N is an integer greater than one. Each first type stage may be implemented with a correlated double-sampling circuit, an auto-zeroing circuit, or a chopper stabilization circuit. Each second type stage may be implemented with a multi-sampling (i.e., double-sampling or higher order sampling) circuit. The multi-stage circuit may be designed to implement a lowpass filter, a DELTASIGMA ADC, or some other circuit.

    9.
    发明专利
    未知

    公开(公告)号：BR0312079A

    公开(公告)日：2007-05-29

    申请号：BR0312079

    申请日：2003-06-26

    Applicant: QUALCOMM INC

    Inventor： KEEHR EDWARD ,  WANG SEAN ,  BAZARJANI SEYFOLLAH

    IPC: H03H19/00 ,  H03M3/00

    Abstract: A digital to analog converter augmented with Direct Charge Transfer (DCT) techniques. A digital to analog converter augmented with DCT and CDS techniques. A digital to analog converter augmented with Postfilter Droop Compensation.

    CONVERTIDOR DE ANALOGO A DIGITAL SIGMA-DELTA CON MUESTREO MULTIPLE.
    10.
    发明专利
    CONVERTIDOR DE ANALOGO A DIGITAL SIGMA-DELTA CON MUESTREO MULTIPLE. 未知

    公开(公告)号：ES2273890T3

    公开(公告)日：2007-05-16

    申请号：ES01973125

    申请日：2001-09-18

    Applicant: QUALCOMM INC

    Inventor： BAZARJANI SEYFOLLAH

    IPC: H03M3/02

    Abstract: Un convertidor analógico a digital sigma-delta, que comprende: al menos un bucle (122), con el bucle, o cada bucle (122) configurado para recibir una señal de entrada al bucle y suministrar una señal de salida del bucle, el bucle, o cada bucle (122) incluye al menos una sección (122A) de bucle, incluyendo cada sección (122A) del bucle, o de cada bucle, una pluralidad de N senderos de señal, en donde cada sendero de señal en una sección específica de bucle está sincronizado por un conjunto de al menos cuatro señales de reloj (CLK1 - CLK4) que tienen fases distintas de aquellas de los restantes senderos de señal en esa específica sección de bucle, y un cuantizador (142) acoplado con cada sección (122A) del bucle, o de cada bucle, estando el cuantizador configurado para recibir y cuantizar una señal desde una última sección de bucle, a fin de suministrar la señal de salida del bucle, caracterizado porque en donde el conjunto de señales de reloj incluye: una primera señal de reloj (CLK1) que tiene una primera fase; una segunda señal de reloj (CLK2) que tiene una segunda fase; una tercera señal de reloj (CLK3) que tiene una tercera fase, siendo dicha tercera señal de reloj (CLK3) complementaria a la primera señal de reloj (CLK1); y una cuarta señal de reloj (CLK4) que tiene una cuarta fase, siendo dicha cuarta señal de reloj (CLK4) complementaria a la segunda señal de reloj (CLK2).

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