公开(公告)号：AU2003209016A8

公开(公告)日：2003-09-02

申请号：AU2003209016

申请日：2003-02-04

Applicant: QUALCOMM INC

Inventor： WALKER BRETT C ,  MOLLENKOPF STEVEN M ,  SEE ANDREW

IPC: H04B1/04 ,  H04L27/20 ,  H03M1/66

Abstract: A transmitter (108) converts a digital baseband signal input (150) for transmission by an antenna (114) to support multiple communication standards. An over-deviation phase multiplier (130) increases signal phase deviation by a factor of M. A digital phase modulator (176) applies trigonometric lookup tables. A digital intermediate frequency up-converter (132) up-shifts frequencies of desired signal content. First and second digital-to-analog converters (DACs) (134) and (136) use relatively low-bit operations, which add DAC noise (212). First and second low pass filters (138) and (140) apply rejection above frequencies of desired signal content. An analog I/Q modulator (142) converts from complex to real signals, adding an unwanted signal spaced from the desired signal content by an intermediate frequency multiple. A limiter (144) reduces amplitude modulated noise. An over-deviation phase divider (146) divides signal phase deviation by 1/M to reduce phase modulated noise.

公开(公告)号：CA2474505A1

公开(公告)日：2003-08-14

申请号：CA2474505

申请日：2003-02-04

Applicant: QUALCOMM INC

Inventor： SEE ANDREW ,  WALKER BRETT C ,  MOLLENKOPF STEVEN M

IPC: H04B1/04 ,  H04L27/20 ,  H03M1/66

Abstract: A transmitter (108) converts a digital baseband signal input (150) for transmission by an antenna (114) to support multiple communication standards. An over-deviation phase multiplier (130) increases signal phase deviation by a factor of M. A digital phase modulator (176) applies trigonometric lookup tables. A digital intermediate frequency up-converter (132) up-shifts frequencies of desired signal content. First and second digital-to-analog converters (DACs) (134) and (136) use relatively low-bit operations, which add DAC noise (212). First and second low pass filters (138) and (140) apply rejection above frequencies of desired signal content. An analog I/Q modulator (142) converts from complex to real signals, adding an unwanted signal spaced from the desired signal content by an intermediate frequency multiple. A limiter (144) reduces amplitude modulated noise. An over-deviation phase divider (146) divides signal phase deviation by 1/M to reduce phase modulated noise.

公开(公告)号：CA2474129A1

公开(公告)日：2003-08-07

申请号：CA2474129

申请日：2003-01-27

Applicant: QUALCOMM INC

Inventor： MOLLENKOPF STEVEN ,  JAFFEE JAMES ,  SEE ANDREW ,  SZABO SANDOR

IPC: H04B1/04 ,  H03C3/09 ,  H03C3/40 ,  H03D7/18 ,  H03L1/00 ,  H03L3/00 ,  H03L7/18 ,  H04B1/40 ,  H03L7/185 ,  H04B1/30

Abstract: A wireless transceiver includes a transmitter having a harmonic rejection mixer and an RF output phase-locked loop in a two step up-conversion architecture, and a direct conversion receiver. The transmitter includes a local oscillator for producing a signal at a multiple of an intermediate frequency, a quadrature modulator harmonic rejection mixer responsive to the signal at the multiple of the intermediate frequency for modulating in-phase and quadrature-phase base-band signals to produce an intermediate frequency signal, a switchable signal responsive to the intermediate frequency signal for producing a filtered intermediate frequency signal, and an RF output offset phase-locked loop responsive to the filtered intermediate frequency signal and the signal at the multiple of the intermediate frequency for producing an RF transmission signal. The harmonic rejection mixer reduces filtering requirements to facilitate a high level of circuit integration whi le the output offset phase-locked loop reduces the power consumption. TheThe switchability of the filter allows the utilisation of the transceiver for EGSM, DCS and PCS communication. The local oscillator may use a integer or fractional-N phase-locked loop.

公开(公告)号：BR0307099A

公开(公告)日：2005-02-01

申请号：BR0307099

申请日：2003-01-27

Applicant: QUALCOMM INC

Inventor： SEE ANDREW ,  JAFFEE JAMES ,  MOLLENKOPF STEVEN ,  SZABO SANDOR

IPC: H04B1/04 ,  H03C3/09 ,  H03C3/40 ,  H03D7/18 ,  H03L1/00 ,  H03L3/00 ,  H03L7/18 ,  H04B1/40 ,  H03L7/185 ,  H04B1/30

Abstract: A wireless transceiver includes a transmitter having a harmonic rejection mixer and an RF output phase-locked loop in a two step up-conversion architecture, and a direct conversion receiver. The transmitter includes a local oscillator for producing a signal at a multiple of an intermediate frequency, a quadrature modulator harmonic rejection mixer responsive to the signal at the multiple of the intermediate frequency for modulating in-phase and quadrature-phase base-band signals to produce an intermediate frequency signal, a filter responsive to the intermediate frequency signal for producing a filtered intermediate frequency signal, and an RF output offset phase-locked loop responsive to the filtered intermediate frequency signal and the signal at the multiple of the intermediate frequency for producing an RF transmission signal. The harmonic rejection mixer reduces filtering requirements to facilitate a high level of circuit integration. The local oscillator may use a integer or fractional-N phase-locked loop.

公开(公告)号：AU2003209016A1

公开(公告)日：2003-09-02

申请号：AU2003209016

申请日：2003-02-04

Applicant: QUALCOMM INC

Inventor： MOLLENKOPF STEVEN M ,  SEE ANDREW ,  WALKER BRETT C

IPC: H04B1/04 ,  H04L27/20 ,  H03M1/66

Abstract: A transmitter (108) converts a digital baseband signal input (150) for transmission by an antenna (114) to support multiple communication standards. An over-deviation phase multiplier (130) increases signal phase deviation by a factor of M. A digital phase modulator (176) applies trigonometric lookup tables. A digital intermediate frequency up-converter (132) up-shifts frequencies of desired signal content. First and second digital-to-analog converters (DACs) (134) and (136) use relatively low-bit operations, which add DAC noise (212). First and second low pass filters (138) and (140) apply rejection above frequencies of desired signal content. An analog I/Q modulator (142) converts from complex to real signals, adding an unwanted signal spaced from the desired signal content by an intermediate frequency multiple. A limiter (144) reduces amplitude modulated noise. An over-deviation phase divider (146) divides signal phase deviation by 1/M to reduce phase modulated noise.

公开(公告)号：WO03067841A3

公开(公告)日：2003-09-12

申请号：PCT/US0303557

申请日：2003-02-04

Applicant: QUALCOMM INC

Inventor： MOLLENKOPF STEVEN M ,  SEE ANDREW ,  WALKER BRETT C

IPC: H04B1/04 ,  H04L27/20 ,  H03M1/66

CPC classification number: H04L27/2017 ,  H04B1/0475 ,  H04L27/2092

Abstract: A transmitter (108) converts a digital baseband signal input (150) for transmission by an antenna (114) to support multiple communication standards. An over-deviation phase multiplier (130) increases signal phase deviation by a factor of M. A digital phase modulator (176) applies trigonometric lookup tables. A digital intermediate frequency up-converter (132) up-shifts frequencies of desired signal content. First and second digital-to-analog converters (DACs) (134) and (136) use relatively low-bit operations, which add DAC noise (212). First and second low pass filters (138) and (140) apply rejection above frequencies of desired signal content. An analog I/Q modulator (142) converts from complex to real signals, adding an unwanted signal spaced from the desired signal content by an intermediate frequency multiple. A limiter (144) reduces amplitude modulated noise. An over-deviation phase divider (146) divides signal phase deviation by 1/M to reduce phase modulated noise.

Abstract translation: 发射机（108）转换数字基带信号输入（150）以供天线（114）发射以支持多种通信标准。 过偏相位乘法器（130）将信号相位偏移增加一个因子M.数字相位调制器（176）应用三角查找表。 数字中频上变频器（132）上变频所需信号内容的频率。 第一和第二数模转换器（DAC）（134）和（136）使用相对较低位的操作，这增加了DAC噪声（212）。 第一和第二低通滤波器（138）和（140）在期望信号内容的频率上施加抑制。 模拟I / Q调制器（142）从复信号转换成实信号，将期望的信号内容间隔不想要的信号加上中​​频倍数。 限幅器（144）降低调幅噪声。 过偏相位分配器（146）将信号相位偏差除以1 / M以减少相位调制噪声。