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公开(公告)号：JP2010193489A
公开(公告)日：2010-09-02
申请号：JP2010085217
申请日：2010-04-01
Applicant: Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
Inventor： LI TAO , HOLENSTEIN CHRISTIAN , KANG INJUP , WALKER BRETT C , PETERZELL PAUL E , CHALLA RAGHU , SEVERSON MATTHEW L , RAGHUPATHY ARUN , SIH GILBERT C
CPC classification number: H03G3/3078 , H03G3/3068 , H03G3/3089
Abstract: PROBLEM TO BE SOLVED: To provide a direct downconversion receiver architecture providing a signal gain and DC offset correction. SOLUTION: The direct downconversion receiver architecture includes: a DC loop to remove DC offset from signal components; a digital variable gain amplifier (DVGA) to provide a range of gains; an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry; and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The operating mode of the VGA loop is selected based on the operating mode of the DC loop, since these two loops interact with each other. The duration of time the DC loop is operated in an acquisition mode is selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. COPYRIGHT: (C)2010,JPO&INPIT
Abstract translation: 要解决的问题：提供一种提供信号增益和DC偏移校正的直接下变频接收机架构。 解决方案：直接下变频接收机架构包括：DC信号消除DC偏移的DC环路; 数字可变增益放大器（DVGA）提供一系列增益; 自动增益控制（AGC）回路，为DVGA和RF /模拟电路提供增益控制; 以及串行总线接口（SBI）单元，通过串行总线提供对RF /模拟电路的控制。 基于DC环路的工作模式选择VGA环路的工作模式，因为这两个环路相互交互。 在采集模式下，DC环路工作的持续时间被选择为与采集模式中的DC环路带宽成反比。 版权所有（C）2010，JPO＆INPIT
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公开(公告)号：JP2009010959A
公开(公告)日：2009-01-15
申请号：JP2008177384
申请日：2008-07-07
Applicant: Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
Inventor： LI TAO , HOLENSTEIN CHRISTIAN , KANG INJUP , WALKER BRETT C , PETERZELL PAUL E , CHALLA RAGHU , SEVERSON MATTHEW L , RAGHUPATHY ARUN , SIH GILBERT C
CPC classification number: H03G3/3078 , H03G3/3068 , H03G3/3089
Abstract: PROBLEM TO BE SOLVED: To provide a direct downconversion receiver architecture capable of providing the required signal gain and DC offset correction. SOLUTION: A direct downconversion receiver architecture has a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus. COPYRIGHT: (C)2009,JPO&INPIT
Abstract translation: 要解决的问题：提供能够提供所需信号增益和DC偏移校正的直接下变频接收机架构。 解决方案：直接下变频接收器架构具有DC环路，用于消除信号分量的DC偏移，提供一系列增益的数字可变增益放大器（DVGA），提供增益控制的自动增益控制（AGC）回路 用于DVGA和RF /模拟电路，以及串行总线接口（SBI）单元，通过串行总线为RF /模拟电路提供控制。 可以基于DC循环的操作模式来选择VGA循环的操作模式，因为这两个循环彼此相互作用。 在采集模式下，DC环路工作的持续时间可以被选择为与采集模式中的DC环路带宽成反比。 一些或全部RF /模拟电路的控制可以通过串行总线提供。 版权所有（C）2009，JPO＆INPIT
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公开(公告)号：JP2008295076A
公开(公告)日：2008-12-04
申请号：JP2008177383
申请日：2008-07-07
Applicant: Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
Inventor： LI TAO , HOLENSTEIN CHRISTIAN , KANG INJUP , WALKER BRETT C , PETERZELL PAUL E , CHALLA RAGHU , SEVERSON MATTHEW L , RAGHUPATHY ARUN , SIH GILBERT C
CPC classification number: H03G3/3078 , H03G3/3068 , H03G3/3089
Abstract: PROBLEM TO BE SOLVED: To obtain a direct down converting receiver architecture having a DC loop for removing a DC offset from a signal component, a digital variable gain amplifier (DVGA) for providing a gain range, an automatic gain control (AGC) loop for performing gain control relating to the DVGA and RF/analog circuits, and a serial bus interface (SBI) unit for providing control relating to the RF/analog circuits via a serial bus. SOLUTION: The DVGA is to be effectively designed and disposed. Since these two loops mutually performs interaction, an operation mode of the VGA loop is to be selected based on an operation mode of the DC loop. Selection is made so as to be in inverse proportion to bandwidth of the DC loop in a captured mode while the DC loop is operated by the captured mode. Control is to be provided to some or all of the RF/analog circuits via the serial bus. COPYRIGHT: (C)2009,JPO&INPIT
Abstract translation: 要解决的问题：为了获得具有用于从信号分量中去除DC偏移的DC回路的直接下变频接收机架构，用于提供增益范围的数字可变增益放大器（DVGA），自动增益控制（AGC） ）环路，用于执行与DVGA和RF /模拟电路相关的增益控制;以及串行总线接口（SBI）单元，用于经由串行总线提供与RF /模拟电路相关的控制。
解决方案：DVGA要有效设计和处理。 由于这两个环路相互进行交互，所以基于DC循环的操作模式来选择VGA环路的操作模式。 在捕捉模式下，直流环路被捕捉模式操作时，进行与直流回路的带宽成反比例的选择。 将通过串行总线向部分或全部RF /模拟电路提供控制。 版权所有（C）2009，JPO＆INPIT
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4.发明专利Continuously variable gain radio frequency driver amplifier having linear in decibel gain control characteristics 审中-公开连续可变增益无线电频率放大器具有线性增益控制特性
公开(公告)号：JP2010273360A
公开(公告)日：2010-12-02
申请号：JP2010152232
申请日：2010-07-02
Applicant: Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
Inventor： BARNETT KENNETH , WALKER BRETT C , GARD KEVIN
CPC classification number: H04B5/00 , H03F1/301 , H03G1/04 , H03G3/3036 , H03G3/3042 , H03G7/001
Abstract: PROBLEM TO BE SOLVED: To provide a radio frequency (RF) driver amplifier system and method that provides linear in decibel gain control.
SOLUTION: An RF driver amplifier system includes a linear transconductor receiving an input voltage and providing a controlled current on the basis of input voltage received, temperature compensation circuitry for varying power from the linear transconductor according to absolute temperature, an exponential current controller receiving power varied according to temperature and providing an exponential current in response, and an inductive degeneration compensator receiving exponential current and providing a control current to driver amplifier circuitry, thereby compensating for inductive degeneration due to at least one inductor in the driver amplifier circuitry. Control current passes from the inductive degeneration compensator to the driver amplifier circuitry.
COPYRIGHT: (C)2011,JPO&INPITAbstract translation: 要解决的问题：提供提供线性分贝增益控制的射频（RF）驱动放大器系统和方法。 解决方案：RF驱动放大器系统包括接收输入电压并基于接收的输入电压提供受控电流的线性跨导器，用于根据绝对温度从线性跨导器改变功率的温度补偿电路，指数电流控制器 接收功率根据温度变化并提供响应的指数电流，以及感应退化补偿器，其接收指数电流并向驱动器放大器电路提供控制电流，从而补偿由于驱动器放大器电路中的至少一个电感器引起的电感变性。 控制电流从感应退化补偿器传递到驱动器放大器电路。 版权所有（C）2011，JPO＆INPIT
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公开(公告)号：JP2010213310A
公开(公告)日：2010-09-24
申请号：JP2010094023
申请日：2010-04-15
Applicant: Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
Inventor： LI TAO , HOLENSTEIN CHRISTIAN , KANG INJUP , WALKER BRETT C , PETERZELL PAUL E , CHALLA RAGHU , SEVERSON MATTHEW L , RAGHUPATHY ARUN , SIH GILBERT C
CPC classification number: H03G3/3078 , H03G3/3068 , H03G3/3089
Abstract: PROBLEM TO BE SOLVED: To provide an architecture of a direct down conversion receiver capable of providing required signal gain and DC offset correction. SOLUTION: The architecture has a DC loop for removing DC offset from a signal component, a digital variable gain amplifier (DVGA) for providing a gain range, an automatic gain control (AGC) loop for performing a gain control relating to the DVGA and an RF/analog circuit, and a serial bus interface (SBI) unit for providing control to the RF/analog circuit via a serial bus. Since these two loops perform mutual interaction with each other in design and disposition of the DVGA, an operation mode of the VGA loop is selected based on an operation mode of the DC loop. Within a time period while the DC loop is operating by a capturing mode, selection is made so as to be operated in inverse proportion to a bandwidth of the DC loop in the capturing mode. The control relating to some or all of RF/analog circuits is provided via the serial bus. COPYRIGHT: (C)2010,JPO&INPIT
Abstract translation: 要解决的问题：提供能够提供所需信号增益和DC偏移校正的直接下变频接收机的架构。 解决方案：该架构具有用于从信号分量中去除DC偏移的直流回路，用于提供增益范围的数字可变增益放大器（DVGA），用于执行与增益范围相关的增益控制的自动增益控制（AGC） DVGA和RF /模拟电路以及串行总线接口（SBI）单元，用于通过串行总线向RF /模拟电路提供控制。 由于这两个循环在DVGA的设计和配置中彼此相互作用，所以基于DC循环的操作模式来选择VGA循环的操作模式。 在DC循环通过捕获模式操作的时间段内，选择在捕获模式中与DC环路的带宽成反比地运行。 通过串行总线提供与RF /模拟电路中的一些或全部相关的控制。 版权所有（C）2010，JPO＆INPIT
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Patent Agency Ranking
公开(公告)号：AU2007224396B2
公开(公告)日：2010-07-08
申请号：AU2007224396
申请日：2007-10-15
Applicant: QUALCOMM INC
Inventor： KANG INJUP , HOLENSTEIN CHRISTIAN , CHALLA RAGHU , WALKER BRETT C , SIH GILBERT C , LI TAO , SEVERSON MATTHEW L , RAGHUPATHY ARUN , PETERZELL PAUL E
Abstract: An apparatus and method in a wireless communication system, the apparatus comprising: first means for amplifying a received signal; means for cancelling a DC offset in the amplified signal; second means for digitally amplifying the DC offset cancelled signal; and means for measuring the digitally amplified signal and to control the gains of the first and second amplifying means.
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公开(公告)号：AU2007224394B2
公开(公告)日：2010-07-08
申请号：AU2007224394
申请日：2007-10-15
Applicant: QUALCOMM INC
Inventor： SIH GILBERT C , KANG INJUP , WALKER BRETT C , LI TAO , PETERZELL PAUL E , SEVERSON MATTHEW L , RAGHUPATHY ARUN , HOLENSTEIN CHRISTIAN , CHALLA RAGHU
Abstract: An apparatus and method in a wireless communication system, the apparatus comprising: first means for amplifying a received signal; means for cancelling a DC offset in the amplified signal; second means for digitally amplifying the DC offset cancelled signal; and means for measuring the digitally amplified signal and to control the gains of the first and second amplifying means.
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公开(公告)号：DE60040932D1
公开(公告)日：2009-01-08
申请号：DE60040932
申请日：2000-11-03
Applicant: QUALCOMM INC
Inventor： WALKER BRETT C , SAHOTA KAMAL GURKANWAL
Abstract: Techniques for adjusting the bias current of an active circuit in a transmitter based on the signal gain of the transmitter. The bias current affects various performances including linearity, noise figure, frequency response, and others. The amount of bias current that provides the required level of performance is dependent on the power level, which can be inferred from the gain control signals used to control the variable gain elements in the transmit signal path. Initially, at least one gain control signal for at least one variable gain element in the transmit signal path is received, with each gain control signal being indicative of an amplitude of a signal to be operated on by the active circuit. The bias current of the active circuit is then adjusted in accordance with the received gain control signal(s). To ensure proper circuit performance, the bias current can be limited to within a range defined by an upper value Imax and a lower value Imin can be set to a percentage of Imax. Imax and Imin can be generated by programmable current sources, and can also be compensated for temperature and power supply variations.
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公开(公告)号：DE60036887D1
公开(公告)日：2007-12-06
申请号：DE60036887
申请日：2000-11-03
Applicant: QUALCOMM INC
Inventor： GARD KEVIN G , SAHOTA KAMAL GURKANWAL , WALKER BRETT C
Abstract: A device for use in a wireless communications system that reduces the amount of phase noise in the carrier signals due to powering down circuit elements for reducing power consumption. The device includes one or more carrier signal generators coupled to a transmitter. Each signal generator provides a respective carrier signal. The transmitter receives and modulates one or more carrier signals with one or more input signals to generate a modulated signal, which is gated on and off during a discontinnous data transmission. The transmitter includes one or more input buffers, with each input buffer receiving and buffering a respective carrier signal. The input buffers are maintained biased for the duration of the data transmission, even as the modulated signal is gated on and off, to provide a constant load for the signal generators and to isolate the carrier signal generators from switching noise. Some other active elements in the transmitter may be powered down when the modulated signal is gated off to further reduce power consumption.
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公开(公告)号：AU2007224394A1
公开(公告)日：2007-11-01
申请号：AU2007224394
申请日：2007-10-15
Applicant: QUALCOMM INC
Inventor： SIH GILBERT C , KANG INJUP , WALKER BRETT C , LI TAO , PETERZELL PAUL E , SEVERSON MATTHEW L , RAGHUPATHY ARUN , HOLENSTEIN CHRISTIAN , CHALLA RAGHU
Abstract: An apparatus and method in a wireless communication system, the apparatus comprising: first means for amplifying a received signal; means for cancelling a DC offset in the amplified signal; second means for digitally amplifying the DC offset cancelled signal; and means for measuring the digitally amplified signal and to control the gains of the first and second amplifying means.
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