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    공유 버스 상의 다수의 동일한 디바이스들의 식별
    1.
    发明公开
    공유 버스 상의 다수의 동일한 디바이스들의 식별 审中-公开

    公开(公告)号：KR20180056718A

    公开(公告)日：2018-05-29

    申请号：KR20187011094

    申请日：2016-08-26

    Applicant: QUALCOMM INC

    Inventor： SENGOKU SHOICHIRO

    IPC: G06F13/364 ,  G06F13/40 ,  G06F13/42 ,  H04L29/12

    CPC classification number: G06F13/364 ,  G06F13/404 ,  G06F13/4282 ,  H04L61/2038 ,  H04L61/2092

    Abstract: 복수의다른동일한슬레이브디바이스들과버스를공유하는슬레이브디바이스들에대하여자체식별시스템이제공된다. 각각의슬레이브디바이스는공유버스와별개이고적어도하나의인접슬레이브디바이스에커플링되는, 2 이상의추가의인터페이스들 (예컨대, 단일라인) 을포함할수도있다. 마스터디바이스와슬레이브디바이스에알려진프로토콜은, 각각의슬레이브디바이스가마스터디바이스와슬레이브디바이스간에고유한식별자를명시적으로송신할필요없이, 자신을식별하게하는데사용된다. 복수의슬레이브디바이스들은마스터디바이스로부터의하나이상의브로드캐스트들에응답하여선택적으로구동되고및/또는약하게풀 업또는풀 다운되는, 제 1 인터페이스와제 2 인터페이스를통해데이지체이닝된다. 그들의제 1 및제 2 인터페이스의상태에기초하여, 슬레이브디바이스는브로드캐스트에응답할수도있고, 따라서마스터디바이스에식별자를암시적으로제공한다.

    인코딩된 멀티-레인 N-팩토리얼 및 다른 멀티-와이어 통신 시스템들
    2.
    发明公开
    인코딩된 멀티-레인 N-팩토리얼 및 다른 멀티-와이어 통신 시스템들 审中-公开

    公开(公告)号：KR20180066065A

    公开(公告)日：2018-06-18

    申请号：KR20187009328

    申请日：2016-09-09

    Applicant: QUALCOMM INC

    Inventor： SENGOKU SHOICHIRO

    IPC: H04L7/00 ,  G06F13/42 ,  H04L25/14 ,  H04L25/49

    CPC classification number: H04L7/0008 ,  G06F13/4291 ,  H04L25/14 ,  H04L25/49

    Abstract: 특히, 전자장치내의 2개의디바이스들사이에서멀티-와이어데이터통신링크를통한데이터의통신을용이하게하는시스템, 방법들및 장치가설명된다. 수신디바이스는멀티-와이어링크를통해심볼들의시퀀스를수신한다. 수신디바이스는전용클록라인을통해클록신호를추가로수신하며, 여기서, 전용클록라인은멀티-와이어링크와는별개이고그와병렬이다. 수신디바이스는, 클록신호를사용하여심볼들의시퀀스를디코딩한다. 일양상에서, 제2 클록신호는, 심볼들의시퀀스내의연속적인심볼들의쌍들사이의보장된트랜지션들에삽입된다. 따라서, 수신디바이스는, 제2 클록신호를무시하면서, 전용클록라인을통해수신된클록신호를사용하여심볼들의시퀀스를디코딩한다.

    Circuito de recuperación de reloj para señales de datos de múltiples cables
    3.
    发明专利
    Circuito de recuperación de reloj para señales de datos de múltiples cables 未知

    公开(公告)号：ES2881302T3

    公开(公告)日：2021-11-29

    申请号：ES14815119

    申请日：2014-11-12

    Applicant: QUALCOMM INC

    Inventor： SENGOKU SHOICHIRO ,  WILEY GEORGE ALAN ,  LEE CHULKYU

    IPC: H04L7/033 ,  H03K5/1252 ,  H03K5/1534 ,  H04L25/14 ,  H04L25/49

    Abstract: Un procedimiento de funcionamiento en un circuito receptor, que comprende: recibir una señal ensanchada distribuida a través de una pluralidad de interfaces de línea, transportando la señal ensanchada símbolos con transiciones de estado de símbolo a símbolo garantizadas entre símbolos consecutivos, estando definida la señal ensanchada por una pluralidad de señales de transición de estado que incluyen una primera señal a través de una primera interfaz de línea y una segunda señal a través de una segunda interfaz de línea; obtener una señal de reloj en base a una comparación de transiciones entre una primera muestra de la primera señal y una segunda muestra retardada de la primera señal, y una comparación de transiciones entre una primera muestra de la segunda señal y una segunda muestra retardada de la segunda señal; y muestrear la segunda muestra retardada de la primera señal en base a la señal de reloj para proporcionar una salida de símbolo.

    CAMERA CONTROL INTERFACE EXTENSION BUS
    4.
    发明专利
    CAMERA CONTROL INTERFACE EXTENSION BUS 未知

    公开(公告)号：CA2911404A1

    公开(公告)日：2014-12-18

    申请号：CA2911404

    申请日：2014-06-12

    Applicant: QUALCOMM INC

    Inventor： SENGOKU SHOICHIRO ,  WILEY GEORGE ALAN ,  CHEUNG JOSEPH

    IPC: G06F13/42

    Abstract: System, methods and apparatus are described that offer improved performance of a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control interface (CCI) operations. CCI extension (CCIe) devices are described. CCIe devices may be configured as a bus master or as a slave. In one method, a CCIe transmitter may generate a transition number from a set of bits, convert the transition number into a sequence of symbols, and transmit the sequence of symbols in the signaling state of a two-wire serial bus. Timing information may be encoded in the transitions between symbols of consecutive pairs of symbols in the sequence of symbols. For example, each transition may cause a change in the signaling state of at least one wire of the two-wire serial bus. A CCIe receiver may derive a receive clock from the transitions in order to receive and decode the sequence of symbols.

    Circuito de control en modo de tensión para sistemas de N fases
    5.
    发明专利
    Circuito de control en modo de tensión para sistemas de N fases 未知

    公开(公告)号：ES2632283T3

    公开(公告)日：2017-09-12

    申请号：ES14713350

    申请日：2014-03-07

    Applicant: QUALCOMM INC

    Inventor： LEE CHULKYU ,  WILEY GEORGE ALAN ,  SENGOKU SHOICHIRO

    IPC: H04B3/06

    Abstract: Un procedimiento de transferencia de datos que comprende: asignar (1202) datos a una secuencia de símbolos que vayan a transmitirse en una pluralidad de cables; codificar (1204) la secuencia de símbolos en tres señales, en la que cada una de las tres señales está en una de tres fases para cada símbolo que vaya a transmitirse y en la que las señales están en fases diferentes entre sí durante la transmisión de cada símbolo; y accionar (1206) cada uno de tres terminales de acuerdo con una de las tres señales, caracterizado por que el accionamiento de cada uno de los tres terminales comprende: encender (1208) un primer transistor (1102) y apagar un segundo transistor (1104) cuando una correspondiente de las tres señales esté en una primera fase, en el que cada uno de los tres terminales se acciona hacia un primer nivel de tensión cuando el primer transistor está encendido; encender (1210) el segundo transistor (1104) y apagar el primer transistor (1102) cuando la correspondiente de las tres señales esté en una segunda fase, en el que cada uno de los tres terminales se acciona hacia un segundo nivel de tensión cuando el segundo transistor está encendido; y apagar (1212) el primer transistor (1102) y el segundo transistor (1104) cuando la correspondiente de las tres señales esté en una tercera fase.

    CAMERA CONTROL INTERFACE EXTENSION BUS
    6.
    发明专利
    CAMERA CONTROL INTERFACE EXTENSION BUS 未知

    公开(公告)号：CA2911401A1

    公开(公告)日：2014-12-18

    申请号：CA2911401

    申请日：2014-06-12

    Applicant: QUALCOMM INC

    Inventor： SENGOKU SHOICHIRO ,  WILEY GEORGE ALAN ,  CHEUNG JOSEPH

    IPC: G06F13/42

    Abstract: System, methods and apparatus are described that offer improved performance of a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control interface (CCI) operations. CCI extension (CCIe) devices are described. CCIe devices may be configured as a bus master or as a slave. In one method, a CCIe transmitter may generate a transition number from a set of bits, convert the transition number into a sequence of symbols, and transmit the sequence of symbols in the signaling state of a two-wire serial bus. Timing information may be encoded in the transitions between symbols of consecutive pairs of symbols in the sequence of symbols. For example, each transition may cause a change in the signaling state of at least one wire of the two-wire serial bus. A CCIe receiver may derive a receive clock from the transitions in order to receive and decode the sequence of symbols.

    METHOD TO ENHANCE MIPI D-PHY LINK RATE WITH MINIMAL PHY CHANGES AND NO PROTOCOL CHANGES
    8.
    发明专利
    METHOD TO ENHANCE MIPI D-PHY LINK RATE WITH MINIMAL PHY CHANGES AND NO PROTOCOL CHANGES 未知

    公开(公告)号：CA2923873A1

    公开(公告)日：2015-04-09

    申请号：CA2923873

    申请日：2014-09-22

    Applicant: QUALCOMM INC

    Inventor： SENGOKU SHOICHIRO

    IPC: H04L25/14 ,  H04L7/033

    Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. A first transition may be detected in a signal carried on a data lane of a data communications link or carried on a timing lane of the data communications link and an edge may be generated on a receiver clock signal based on the first transition. Data may be captured from the data lane using the receiver clock signal. The timing lane may carry a clock signal, a strobe signal or another signal providing timing information. The strobe signal may transition between signaling states when no state transition occurs on any of a plurality of data lanes at a boundary between consecutive data periods.

    Multi-lane N-factorial encoded and other multi-wire communication systems
    10.
    发明专利
    Multi-lane N-factorial encoded and other multi-wire communication systems 未知

    公开(公告)号：AU2016335548A1

    公开(公告)日：2018-04-12

    申请号：AU2016335548

    申请日：2016-09-09

    Applicant: QUALCOMM INC

    Inventor： SENGOKU SHOICHIRO

    IPC: H04L7/00 ,  G06F13/42 ,  H04L25/14 ,  H04L25/49

    Abstract: System, methods and apparatus are described that facilitate communication of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A receiving device receives a sequence of symbols over a multi-wire link. The receiving device further receives a clock signal via a dedicated clock line, wherein the dedicated clock line is separate from, and in parallel with, the multi-wire link. The receiving device decodes the sequence of symbols using the clock signal. In an aspect, a second clock signal is embedded in guaranteed transitions between pairs of consecutive symbols in the sequence of symbols. Accordingly, the receiving device decodes the sequence of symbols using the clock signal received via the dedicated clock line while ignoring the second clock signal.

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