公开(公告)号：SG11201902036YA

公开(公告)日：2019-05-30

申请号：SG11201902036Y

申请日：2017-09-23

Applicant: QUALCOMM INC

Inventor： LONCKE VINCENT ,  VARATKAR GIRISH ,  RICHARDSON THOMAS JOSEPH ,  CAO YI

IPC: H03M13/11

Abstract: INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property :::` , 1#111011110111010101111101 110 1 00111111E MIMI! I 1111011110111111 Organization International Bureau (10) International Publication Number 03 (43) International Publication Date .....•\"\"- WO 2018/084956 Al 11 May 2018 (11.05.2018) WIPO I PCT (51) International Patent Classification: (72) Inventors: LONCKE, Vincent; 5775 Morehouse Drive, H03M 13/11 (2006.01) San Diego, California 92121-1714 (US). VARATKAR, (21) International Application Number: Girish; 5775 Morehouse Drive, San Diego, California PCT/US2017/053128 92121-1714 (US). RICHARDSON, Thomas Joseph; 5775 Morehouse Drive, San Diego, California 92121-1714 (US). (22) International Filing Date: CAO, Yi; 5775 Morehouse Drive, San Diego, California 23 September 2017 (23.09.2017) 92121-1714 (US). (25) Filing Language: English (74) Agent: READ, Randol W. et al.; Patterson & Sheridan, (26) Publication Language: English L.L.P., 24 Greenway Plaza, Suite 1600, Houston, Texas 77046 (US). (30) Priority Data: (81) Designated States (unless otherwise indicated, for every 62/416,584 02 November 2016 (02.11.2016) US kind of national protection available): AE, AG, AL, AM, 15/712,845 22 September 2017 (22.09.2017) US AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, (71) Applicant: QUALCOMM INCORPORATED [US/US]; CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, ATTN: International IP Administration, 5775 Morehouse DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, Drive, San Diego, California 92121-1714 (US). HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, — (54) Title: PIPELINED HIGH-THROUGHPUT = (prior's) Bit LLR's LAYERED LDPC DECODER ARCHITECTURE Update bit LLR's — \ ‘;' • '','. • \ \:\ ;\. ••• \ Pass updated LLR's to a — Update posteriori compute stage = after 3 cycle pipeline delay = 1 bit LLR's with Ro f Update bit LLR's with R2/ = Compute a posteriori LLR's — Rn 1 1