公开(公告)号：KR20180021729A

公开(公告)日：2018-03-05

申请号：KR20177037535

申请日：2016-04-27

Applicant: QUALCOMM INC

Inventor： SUH JUNGWON ,  WEST DAVID IAN

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G11C29/52

Abstract: 저전력메모리서브-시스템의메모리어레이및 링크에러정정방법은, 통상적인기입동작및 판독동작동안, 미사용된데이터마스크비트들내에에러정정코드(ECC) 패리티비트들을삽입하는단계를포함한다. 방법은또한, 마스크기입동작동안어써팅(assert)된데이터마스크에대응하는마스크기입데이터바이트에 ECC 패리티비트들을삽입하는단계를포함한다.

Abstract translation: 低功率存储器子系统的存储器阵列和链路纠错方法包括在正常的写入和读取操作期间在未使用的数据屏蔽位中插入纠错码（ECC）奇偶校验位。 该方法还包括在掩码写入操作期间将ECC奇偶校验位插入对应于所声明的数据掩码的掩码写入数据字节中。

公开(公告)号：AU2016355459A1

公开(公告)日：2018-05-10

申请号：AU2016355459

申请日：2016-09-28

Applicant: QUALCOMM INC

Inventor： WEST DAVID IAN ,  SUH JUNGWON

IPC: G06F11/10

Abstract: A memory sub-system may include a memory controller having error correction code (ECC) encoder/decoder logic. The memory controller may be configured to embed link ECC parity bits in unused data mask bits and/or in a mask write data during a mask write operation. The memory controller may also be configured to protect at least a location of the link ECC parity bits during the mask write operation.

公开(公告)号：AU2016355460A1

公开(公告)日：2018-05-10

申请号：AU2016355460

申请日：2016-09-28

Applicant: QUALCOMM INC

Inventor： SUH JUNGWON ,  WEST DAVID IAN

IPC: G06F11/10

Abstract: A memory device may include link error correction code (ECC) decoder and correction circuitry. The ECC decoder and correction circuitry may be arranged in a write path and configured for link error detection and correction of write data received over a data link. The memory device may also include memory ECC encoder circuitry. The memory ECC encoder circuitry may be arranged in the write path and configured for memory protection of the write data during storage in a memory array.

公开(公告)号：AU2016285702A1

公开(公告)日：2017-11-30

申请号：AU2016285702

申请日：2016-04-27

Applicant: QUALCOMM INC

Inventor： SUH JUNGWON ,  WEST DAVID IAN

IPC: G06F11/10

Abstract: A method of memory array and link error correction in a low power memory sub-system includes embedding error correction code (ECC) parity bits within unused data mask bits during a normal write operation and during a read operation. The method also includes embedding the ECC parity bits in a mask write data byte corresponding to an asserted data mask bit during a mask write operation.

公开(公告)号：CA2932653A1

公开(公告)日：2015-07-16

申请号：CA2932653

申请日：2015-01-08

Applicant: QUALCOMM INC

Inventor： WEST DAVID IAN ,  BRUNOLLI MICHAEL JOSEPH ,  CHUN DEXTER TAMIO ,  SRINIVAS VAISHNAV

IPC: G06F11/10 ,  G06F12/00

Abstract: Dynamic random access memory (DRAM) backchannel communication systems and methods are disclosed. In one aspect, a backchannel communication system allows a DRAM to communicate error correction information and refresh alert information to a System on a Chip (SoC), applications processor (AP), or other memory controller.

公开(公告)号：WO2014137710A3

公开(公告)日：2014-11-06

申请号：PCT/US2014018792

申请日：2014-02-26

Applicant: QUALCOMM INC

Inventor： SRINIVAS VAISHNAV ,  KIM ROBERT WON CHOL ,  CLOVIS PHILIP MICHAEL ,  WEST DAVID IAN

IPC: G06F17/50

CPC classification number: H01L27/0207 ,  G06F17/5072 ,  G06F2217/40

Abstract: An integrated circuit includes core logic and a plurality of interface blocks disposed about a periphery of the core logic. A plurality of input or output (I/O) circuits is assigned to one of the plurality of interface blocks. The I/O circuits include external I/O circuits coupled to a device other than the integrated circuit and internal I/O circuits coupled to the integrated circuit. Each interface block includes a first plurality of I/O circuits disposed on a first side of the interface block and a second plurality of I/O circuits disposed on a second side of the interface block. Each interface block also includes interface logic for the interface block between the first plurality of I/O circuits and the second plurality of I/O circuits, and a logic hub that includes a clock distribution of minimal length that drives launch logic and capture logic to form the I/O circuits of the interface block.

Abstract translation: 集成电路包括核心逻辑和围绕核心逻辑的外围设置的多个接口块。 多个输入或输出（I / O）电路被分配给多个接口块中的一个。 I / O电路包括耦合到集成电路以外的器件的外部I / O电路和耦合到集成电路的内部I / O电路。 每个接口块包括设置在接口块的第一侧上的第一多个I / O电路和设置在接口块的第二侧上的第二多个I / O电路。 每个接口块还包括用于在第一多个I / O电路和第二多个I / O电路之间的接口块的接口逻辑，以及逻辑集线器，其包括驱动启动逻辑和捕获逻辑的最小长度的时钟分配 形成接口块的I / O电路。

公开(公告)号：WO2014036456A3

公开(公告)日：2014-04-17

申请号：PCT/US2013057613

申请日：2013-08-30

Applicant: QUALCOMM INC

Inventor： SRINIVAS VAISHNAV ,  YANG BERNIE JORD ,  BRUNOLLI MICHAEL ,  WEST DAVID IAN ,  PAYNTER CHARLES DAVID

IPC: H01L23/522 ,  H01L21/60 ,  H01L21/66 ,  H01L23/485 ,  H01L23/50

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L22/32 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/0556 ,  H01L2224/05569 ,  H01L2224/11462 ,  H01L2224/13028 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/14165 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/27462 ,  H01L2224/29028 ,  H01L2224/29078 ,  H01L2224/29147 ,  H01L2224/3012 ,  H01L2224/3213 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/07802 ,  H01L2924/381 ,  H01L2924/0105 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: Various aspects of an approach for routing die signals in an interior portion of a die (152) using external interconnects (202+222+212) are described herein. The approach provides for contacts (102, 112) coupled to circuits in the interior portion of the die (152), where the contacts (102, 112) are exposed to an exterior portion of the die (152). The external interconnects (202+222+212) are configured to couple these contacts (102, 112) so that signals from the circuits in the interior portion of the die (152) may be routed externally to the die (152) to reinsert them back into the die (152). In various aspects of the disclosed approach, the external interconnects (202+222+212) are protected by a packaging (252) for the die (152). A testing circuit configured to couple the circuits during a testing mode may be foreseen in the interior portion of the die (152).

Abstract translation: 本文描述了使用外部互连（202 + 222 + 212）在管芯（152）的内部部分中布线管芯信号的方法的各个方面。 该方法提供了联接到管芯（152）的内部部分中的电路的触点（102,112），其中触点（102,112）暴露于管芯（152）的外部部分。 外部互连（202 + 222 + 212）被配置为联接这些触点（102,112），使得来自模具（152）的内部部分中的电路的信号可以被外部引导到模具（152）以重新插入 回到模具（152）中。 在所公开的方法的各个方面，外部互连（202 + 222 + 212）由用于管芯（152）的封装（252）保护。 配置成在测试模式期间耦合电路的测试电路可以在模具（152）的内部部分中预见。