公开(公告)号：HK1232339A1

公开(公告)日：2018-01-05

申请号：HK17105914

申请日：2017-06-14

Applicant: QUALCOMM INC

Inventor： LAN JE HSIUNG JEFFREY ,  ZHANG WENYUE ,  DU YANG ,  LEE YONG JU ,  GU SHIQUN ,  XIE JING

IPC: H01L20060101

公开(公告)号：SG11201700918RA

公开(公告)日：2017-04-27

申请号：SG11201700918R

申请日：2015-09-08

Applicant: QUALCOMM INC

Inventor： LAN JE-HSIUNG JEFFREY ,  ZHANG WENYUE ,  DU YANG ,  LEE YONG JU ,  GU SHIQUN ,  XIE JING

IPC: H01L21/822 ,  H01L21/683 ,  H01L27/06

Abstract: A microelectromechanical system (MEMS) bond release structure is provided for manufacturing of three-dimensional integrated circuit (3D IC) devices with two or more tiers. The MEMS bond release structure includes a MEMS sacrificial release layer which may have a pillar or post structure, or alternatively, a continuous sacrificial layer for bonding and release.

公开(公告)号：WO2014085685A3

公开(公告)日：2014-12-24

申请号：PCT/US2013072374

申请日：2013-11-27

Applicant: QUALCOMM INC

Inventor： XIE JING ,  DU YANG

IPC: G06F17/50 ,  G06F1/32 ,  H03K19/00

CPC classification number: G06F17/5072 ,  G06F1/32 ,  G06F1/3287 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5068 ,  G06F17/5077 ,  G06F2217/62 ,  G11C5/14 ,  H01L23/5226 ,  H01L2924/0002 ,  H03K19/0008 ,  H01L2924/00

Abstract: The disclosed embodiments comprise a multi-stage circuit (10) operating across different power domains (A, B). The multi-stage circuit may be implemented as a master-slave flip-flop circuit (10c) integrated with a level shifter (65c) that transfers data across different power domains. The master and slave stages of the flip-flop may be split across two tiers (102, 104) of a 3D IC and may include (i) a level shifter across different power domain integrated within the flip-flop circuit, (ii) reduced one-state writing delays by a self-induced power collapsing technique, (iii) splitting flip-flop power supplies in different tiers using monolithic 3D IC technology, and (iv) cross power domain data transfer between 3D IC tiers.

Abstract translation: 所公开的实施例包括跨越不同功率域（A，B）工作的多级电路（10）。 多级电路可以实现为与在不同电源域上传送数据的电平移位器（65c）集成的主从触发器电路（10c）。 触发器的主从级可分为3D IC的两层（102,104），并且可以包括（i）跨触发器电路中集成的不同功率域的电平移位器，（ii）减少 （iii）使用单片3D IC技术分割不同层级的触发器电源，以及（iv）3D IC层之间的跨功率域数据传输。