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公开(公告)号：KR20120091406A
公开(公告)日：2012-08-17
申请号：KR20127016879
申请日：2009-03-07
Applicant: QUALCOMM INC
Inventor： CHAUDHURI ARUNAVA , YAO IWEN , LIN JEREMY H , GURSKI REMI , YEN KEVIN W
CPC classification number: G06F9/3879 , G06F15/7814
Abstract: 플렉시블하고 재구성가능한 디지털 시스템(예를 들어, 무선 모뎀)은 서브회로들의 세트를 포함한다. 각각의 서브회로는 태스크 매니저 및 데이터 스트림에 대해 한 타입의 동작을 수행하기 위한 소정량의 구성가능한 하드웨어 회로를 포함한다. 서브회로의 태스크 매니저는 서브회로의 구성가능한 하드웨어를 구성 및 제어할 수 있다. 중앙 프로세서는 강결합 메모리 내에 태스크 리스트들의 세트를 유지함으로써 서브회로들의 동작을 구성 및 조작한다. 각각의 태스크 리스트는 대응하는 서브회로에 대한 태스크 명령들을 포함한다. 서브회로의 태스크 매니저는 그것의 태스크 리스트로부터 태스크 명령들을 판독하고, 상기 명령들에 의해 지시되는 바와 같은 그것의 연관된 하드웨어 회로를 제어한다. 타임스탬프 태스크 명령 및 푸시 태스크 명령 및 태스크 리스트 아키텍처는 모뎀 서브회로들로 하여금 제 1 무선 인터페이스 표준 또는 제 2 무선 인터페이스 표준에 따라 동작하도록 용이하게 재구성되게 한다.
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公开(公告)号：JP2013128301A
公开(公告)日：2013-06-27
申请号：JP2013008335
申请日：2013-01-21
Applicant: Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
Inventor： ALI ROSTAMPISHEH , RAGHU N CHALLA , YAO IWEN , DAVIE J SANTOS , MRINAL M NATH
CPC classification number: H03M13/2785 , H03M13/2764 , H03M13/2771 , H03M13/2775 , H03M13/6566
Abstract: PROBLEM TO BE SOLVED: To provide a de-interleaving method based on a multi-banked memory.SOLUTION: A de-interleaver generates a plurality of De-interleaved Reorder Physical (DRP) addresses to simultaneously write a corresponding plurality of LLR values into a multi-banked memory such that not more than one LLR value is written into each bank of the multi-banked memory at a time. By a sequence of such parallel writes, the LLR values of a transmission of a sub-packet are stored in the memory. Address translation performed during generation of the DRP addresses causes the LLR values to be stored within the banks so that a decoder can read the LLR values out of the memory in a de-interleaved sequence. The ability to simultaneously write to multiple LLR values is used to clear locations in a fast and efficient manner.
Abstract translation: 要解决的问题：提供一种基于多存储存储器的解交织方法。 解交织器解交织器产生多个去交织重排物理（DRP）地址，以将对应的多个LLR值同时写入多存储存储器，使得不多于一个LLR值被写入每个存储体 的多存储内存。 通过这种并行写入的顺序，子分组的传输的LLR值被存储在存储器中。 在生成DRP地址期间执行的地址转换导致LLR值被存储在存储体中，使得解码器可以以解交织的顺序从存储器读出LLR值。 用于同时写入多个LLR值的能力用于以快速有效的方式清除位置。 版权所有（C）2013，JPO＆INPIT
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公开(公告)号：JP2013255244A
公开(公告)日：2013-12-19
申请号：JP2013147120
申请日：2013-07-12
Applicant: QUALCOMM INC
Inventor： ALI ROSTAMPISHEH , RAGHU N CHALLA , YAO IWEN , DAVIE J SANTOS , MRINAL M NATH
Abstract: PROBLEM TO BE SOLVED: To provide fast and efficient interleaving.SOLUTION: A de-interleaver generates a plurality of De-interleaved Reorder Physical (DRP) addresses to simultaneously write a corresponding plurality of LLR values into a multi-banked memory such that not more than one LLR value is written into each bank of the multi-banked memory at a time. A sequence of such parallel writes results in the LLR values of transmission of a sub-packet being stored in the memory. Address translation performed during generation of the DRP addresses causes the LLR values to be stored within the banks so that a decoder can read LLR values out of the memory in a de-interleaved sequence. Each memory location of a bank is a word-location for storing multiple related LLR values, where one LLR value is stored along with its parity values.
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公开(公告)号：JP2013038788A
公开(公告)日：2013-02-21
申请号：JP2012189092
申请日：2012-08-29
Applicant: Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
Inventor： TAMER A KADOUS , YAO IWEN , WANG JIBING , JING WEIHONG , LI YONG
CPC classification number: H04L25/061 , H03G3/3068 , H03G3/3078
Abstract: PROBLEM TO BE SOLVED: To perform AGC and DC compensation in a receiver.SOLUTION: A receiver comprises: an energy estimator for generating an estimate of the level of a received signal; an RF device to apply gain to the received signal; an AGC for controlling the RF device gain on the basis of the energy estimate; a first DC compensation loop for finely adjusting DC compensation of the received signal in a fast or slow tracking mode (FTM or STM); and a second DC compensation loop for coarsely adjusting a DC component of the received signal. AGC operations have three modes, namely, in acquisition, in connection, and in sleep.
Abstract translation: 要解决的问题：在接收机中执行AGC和DC补偿。 解决方案：接收机包括：用于产生接收信号的电平的估计的能量估计器; 用于向接收到的信号施加增益的RF设备; 用于基于能量估计来控制RF设备增益的AGC; 用于以快速或慢速跟踪模式（FTM或STM）精细调整接收信号的DC补偿的第一DC补偿环路; 以及用于粗调整接收信号的DC分量的第二DC补偿回路。 AGC操作有三种模式，即在采集，连接和睡眠中。 版权所有（C）2013，JPO＆INPIT
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公开(公告)号：CA2439573A1
公开(公告)日：2002-09-06
申请号：CA2439573
申请日：2002-02-26
Applicant: QUALCOMM INC
Inventor： YAO IWEN , SHIU DA-SHAN
Abstract: Techniques to efficiently generate memory addresses for a Turbo code interleaver using a number of look-up tables. An interleaver includes a storage unit, sets of tables, and an address generator. The storage unit stores K elements for a data packet at locations representative of an RxC array, with the elements being stored in a first (e.g., linear) order and provided in a second (e.g., interleaved) order. A first set of table(s) stor es sequences (e.g., inter-row permutation sequences PA, PB, PC and PD) used to perform row permutation of the array to map from the first order to the seco nd order. A second set of table(s) stores sequences (e.g., intra-row base sequences and prime number sequences) used to perform column permutation. Th e address generator receives a first address for the first order and generates a corresponding second address for the second order based on sequences stored in the tables.
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Patent Agency Ranking
公开(公告)号：CA2718235C
公开(公告)日：2016-07-19
申请号：CA2718235
申请日：2009-03-09
Applicant: QUALCOMM INC
Inventor： KADOUS TAMER A , YAO IWEN , WANG JIBING , JING WEIHONG , LI YONG
IPC: H04L25/06
Abstract: A technique for performing AGC and DC compensation in a receiver. The receiver comprises an energy estimator for generating an estimate of the level of a received signal; an RF device to apply gain to the received signal; an AGC for controlling the RF device gain based on the energy estimation; a first DC compensation loop for finely adjusting the DC component of the received signal in fast or slow tracking mode (FTM or STM); and a second DC compensation loop for coarsely adjusting the DC component of the received signal. Three modes of AGC operations: In Acquisition, iterations of FTM fine DC adjustment, short energy estimation, and RF device gain adjustment are performed during signal timing detection. In Connected, long energy estimation, RF device gain adjustment, and STM fine and coarse DC adjustments are performed during superframe preamble. In Sleep, FTM fine DC adjustment, short energy estimation, and RF device gain adjustment are performed during superframe preamble.
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公开(公告)号：BR0207669A
公开(公告)日：2005-02-01
申请号：BR0207669
申请日：2002-02-26
Applicant: QUALCOMM INC
Inventor： YAO IWEN , SHIU DA-SHAN
Abstract: Techniques to efficiently generate memory addresses for a Turbo code interleaver using a number of look-up tables. An interleaver includes a storage unit, sets of tables, and an address generator. The storage unit stores K elements for a data packet at locations representative of an RxC array, with the elements being stored in a first (e.g., linear) order and provided in a second (e.g., interleaved) order. A first set of table(s) stores sequences (e.g., inter-row permutation sequences PA, PB, PC, and PD) used to perform row permutation of the array to map from the first order to the second order. A second set of table(s) stores sequences (e.g., intra-row base sequences and prime number sequences) used to perform column permutation. The address generator receives a first address for the first order and generates a corresponding second address for the second order based on sequences stored in the tables.
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公开(公告)号：BRPI0909371A2
公开(公告)日：2016-07-26
申请号：BRPI0909371
申请日：2009-03-09
Applicant: QUALCOMM INC
Inventor： YAO IWEN , WANG JIBING , KADOUS TAMER A , JING WEIHONG , LI YONG
IPC: H04L25/06
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公开(公告)号：CA2718235A1
公开(公告)日：2009-10-08
申请号：CA2718235
申请日：2009-03-09
Applicant: QUALCOMM INC
Inventor： KADOUS TAMER A , YAO IWEN , WANG JIBING , JING WEIHONG , LI YONG
IPC: H04L25/06
Abstract: A technique for performing AGC and DC compensation in a receiver. The receiver comprises an energy estimator for generating an estimate of the level of a received signal; an RF device to apply gain to the received signal; an AGC for controlling the RF device gain based on the energy estimation; a first DC compensation loop for finely adjusting the DC component of the received signal in fast or slow tracking mode (FTM or STM); and a second DC compensation loop for coarsely adjusting the DC component of the received signal. Three modes of AGC operations: In Acquisition, iterations of FTM fine DC adjustment, short energy estimation, and RF device gain adjustment are performed during signal timing detection. In Connected, long energy estimation, RF device gain adjustment, and STM fine and coarse DC adjustments are performed during superframe preamble. In Sleep, FTM fine DC adjustment, short energy estimation, and RF device gain adjustment are performed during superframe preamble.
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公开(公告)号：BR0209559A
公开(公告)日：2004-06-15
申请号：BR0209559
申请日：2002-05-09
Applicant: QUALCOMM INC
Inventor： SHIU DA-SHAN , YAO IWEN
Abstract: A buffer structure for storing intermediate results (i.e., APP data) for a Turbo decoder to increase access throughput, the buffer structure is designed to support concurrent access of APP data for two or more bits for each access cycle. This is achieved by partitioning the buffer into a number of banks, with each bank being independently accessible. To avoid access contentions, the banks are assigned to the rows and columns of a 2-dimensional array used for code interleaving such that APP data for consecutive bits are accessed from different banks. To support "linear" addressing, the banks can be arranged into two sets, which are assigned to even-numbered and odd-number columns of the array. To support "interleaved" addressing, the banks can be assigned to groups of rows of the array such that adjacent rows in the interleaved array are assigned to different groups.
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