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    MULTI-CHANNEL AUDIO ALIGNMENT SCHEMES
    1.
    发明申请
    MULTI-CHANNEL AUDIO ALIGNMENT SCHEMES 审中-公开
    多通道音频对齐方案

    公开(公告)号：WO2016076990A1

    公开(公告)日：2016-05-19

    申请号：PCT/US2015/054863

    申请日：2015-10-09

    Applicant: QUALCOMM INCORPORATED

    Inventor： HARIHARAN, Magesh ,  AMARILIO, Lior ,  ARCEO, Julio ,  BALATSOS, Aris ,  GRUBER, Hans Georg

    IPC: H04R5/04 ,  G06F3/16 ,  G06F13/42 ,  H04M1/60

    CPC classification number: H04L65/4069 ,  G06F3/162 ,  G06F13/4291 ,  H04R3/12 ,  H04R5/04 ,  H04R2420/09 ,  H04R2499/11

    Abstract: Multi-channel audio alignment schemes are disclosed. One aspect of the present disclosure provides for accumulation of audio samples across multiple related audio channels at an audio source. Related audio channels indicate their interrelatedness, and when all the related audio channels have data to transmit, the source releases the data onto the time slots of the Serial Low-power Inter-chip Media Bus (SLIMbus), such that the related audio channels are within a given segment window of the time slot. This accumulation is repeated at the boundary of every segment window. Similarly, accumulation may be performed at the audio sink. Components within the audio sink may only read received data if status signals from all related sinks indicate that predefined thresholds have been reached. By providing such accumulation options, audio fidelity is maintained across multiple audio data channels.

    Abstract translation: 公开了多声道音频对准方案。 本公开的一个方面提供了在音频源处跨越多个相关音频声道的音频样本的累积。 相关音频通道指示它们之间的相互关系，并且当所有相关音频通道都有数据要传输时，源将数据释放到串行低功耗片间媒体总线（SLIMbus）的时隙上，使得相关音频通道 在时隙的给定分段窗口内。 这个累积在每个分段窗口的边界处重复。 类似地，可以在音频接收器处执行累积。 如果来自所有相关接收器的状态信号指示已达到预定义阈值，则音频接收器内的组件只能读取接收到的数据。 通过提供这种累积选项，可以在多个音频数据通道中保持音频保真度。

    WAKING A MEDIA BUS
    2.
    发明申请
    WAKING A MEDIA BUS 审中-公开
    调用媒体总线

    公开(公告)号：WO2012149298A1

    公开(公告)日：2012-11-01

    申请号：PCT/US2012/035428

    申请日：2012-04-27

    Applicant: QUALCOMM INCORPORATED ,  GRUBER, Hans Georg ,  ARCEO, Julio ,  HARIHARAN, Magesh ,  MOHAN, Suren

    Inventor： GRUBER, Hans Georg ,  ARCEO, Julio ,  HARIHARAN, Magesh ,  MOHAN, Suren

    IPC: G06F13/42

    CPC classification number: G06F13/4291 ,  G06F1/04 ,  G06F11/0763 ,  G06F11/1658

    Abstract: Arrangements for restarting data transmission on a serial low-power inter-chip media bus (SLIMbus) are presented. A clock signal may be provided in an active mode to a component communicatively coupled with the SLIMbus. Immediately prior to the clock signal in the active mode being provided, the clock signal may have been in a paused mode. While the clock signal was in the paused mode at least until the clock signal is provided in the active mode, the data line may have been inactive (e.g., a toggle on the data line may not have been present). Frame synchronization data for a frame may be transmitted. The frame synchronization data for the frame, as received by the component, may not match expected frame synchronization data. Payload data may be transmitted as part of the frame to the component, wherein the payload data is expected to be read properly by the component.

    Abstract translation: 介绍了在串行低功耗芯片间媒体总线（SLIMbus）上重新启动数据传输的安排。 可以以活动模式将时钟信号提供给与SLIMbus通信耦合的组件。 紧接在提供处于活动模式的时钟信号之前，时钟信号可能已经处于暂停模式。 至少在时钟信号处于激活模式之前，时钟信号处于暂停模式，数据线可能已经不工作（例如，数据线上的切换可能不存在）。 可以发送帧的帧同步数据。 由组件接收的帧的帧同步数据可能不匹配预期的帧同步数据。 有效负载数据可以作为帧的一部分被发送到组件，其中预期有效载荷数据被组件正确地读取。

    NON-PORTED GENERIC DEVICE (SOFTWARE MANAGED GENERIC DEVICE)
    4.
    发明申请
    NON-PORTED GENERIC DEVICE (SOFTWARE MANAGED GENERIC DEVICE) 审中-公开
    非定制通用设备（软件管理的一般设备）

    公开(公告)号：WO2012149311A1

    公开(公告)日：2012-11-01

    申请号：PCT/US2012/035446

    申请日：2012-04-27

    Applicant: QUALCOMM INCORPORATED ,  GRUBER, Hans Georg ,  ARCEO, Julio ,  HARIHARAN, Magesh ,  MOHAN, Suren ,  LANDGUTH, Mark A.

    Inventor： GRUBER, Hans Georg ,  ARCEO, Julio ,  HARIHARAN, Magesh ,  MOHAN, Suren ,  LANDGUTH, Mark A.

    IPC: G06F13/42

    CPC classification number: G06F13/4291

    Abstract: Techniques are disclosed for utilizing a non-ported generic device (NGD) or other non-ported hardware to couple processing device(s) to access components on a serial data bus without the need for integrated manager hardware. Using the NGD, a processing device(s) can utilize available unused bandwidth on the serial data bus to communicate with components coupled with the serial data bus, including a processing device having the manager hardware. Various alterations and embodiments are disclosed.

    Abstract translation: 公开了利用非移植通用设备（NGD）或其他非端口硬件将处理设备耦合到访问串行数据总线上的组件而不需要集成管理器硬件的技术。 使用NGD，处理设备可以利用串行数据总线上的可用未使用的带宽与与串行数据总线耦合的组件进行通信，包括具有管理器硬件的处理设备。 公开了各种改变和实施例。

    MULTI-CHANNEL AUDIO ALIGNMENT SCHEMES
    5.
    发明公开
    MULTI-CHANNEL AUDIO ALIGNMENT SCHEMES 审中-公开
    多通道音频对齐方案

    公开(公告)号：EP3219111A1

    公开(公告)日：2017-09-20

    申请号：EP15788251.5

    申请日：2015-10-09

    Applicant: Qualcomm Incorporated

    Inventor： HARIHARAN, Magesh ,  AMARILIO, Lior ,  ARCEO, Julio ,  BALATSOS, Aris ,  GRUBER, Hans Georg

    IPC: H04R5/04 ,  G06F3/16 ,  G06F13/42 ,  H04M1/60

    CPC classification number: H04L65/4069 ,  G06F3/162 ,  G06F13/4291 ,  H04R3/12 ,  H04R5/04 ,  H04R2420/09 ,  H04R2499/11

    Abstract: Multi-channel audio alignment schemes are disclosed. One aspect of the present disclosure provides for accumulation of audio samples across multiple related audio channels at an audio source. Related audio channels indicate their interrelatedness, and when all the related audio channels have data to transmit, the source releases the data onto the time slots of the Serial Low-power Inter-chip Media Bus (SLIMbus), such that the related audio channels are within a given segment window of the time slot. This accumulation is repeated at the boundary of every segment window. Similarly, accumulation may be performed at the audio sink. Components within the audio sink may only read received data if status signals from all related sinks indicate that predefined thresholds have been reached. By providing such accumulation options, audio fidelity is maintained across multiple audio data channels.

    Abstract translation: 公开了多声道音频对齐方案。 本公开的一个方面提供了在音频源处跨越多个相关音频声道的音频样本的累积。 相关音频通道指示它们之间的相互关系，并且当所有相关音频通道都有数据要传输时，源将数据释放到串行低功耗片间媒体总线（SLIMbus）的时隙上，使得相关音频通道 在时隙的给定分段窗口内。 这个累积在每个分段窗口的边界处重复。 类似地，可以在音频接收器处执行累积。 如果来自所有相关接收器的状态信号指示已达到预定义阈值，则音频接收器内的组件只能读取接收到的数据。 通过提供这样的累积选项，跨多个音频数据信道保持音频保真度。

    MULTI-CHANNEL AUDIO ALIGNMENT SCHEMES
    7.
    发明申请
    MULTI-CHANNEL AUDIO ALIGNMENT SCHEMES 审中-公开
    多声道音频对准方案

    公开(公告)号：WO2016076989A1

    公开(公告)日：2016-05-19

    申请号：PCT/US2015/054861

    申请日：2015-10-09

    Applicant: QUALCOMM INCORPORATED

    Inventor： HARIHARAN, Magesh ,  AMARILIO, Lior ,  ARCEO, Julio ,  BALATSOS, Aris ,  GRUBER, Hans Georg

    IPC: H04R5/04 ,  G06F3/16 ,  G06F13/42 ,  H04M1/60

    CPC classification number: H04L65/4069 ,  G06F3/162 ,  G06F3/165 ,  G06F13/4291 ,  H04L65/604 ,  H04R3/12 ,  H04R5/04 ,  H04R2420/09 ,  H04R2499/11

    Abstract: Multi-channel audio alignment schemes are disclosed. One aspect of the present disclosure provides for accumulation of audio samples across multiple related audio channels at an audio source. Related audio channels indicate their interrelatedness, and when all the related audio channels have data to transmit, the source releases the data onto the time slots of the Serial Low-power Inter-chip Media Bus (SLIMbus), such that the related audio channels are within a given segment window of the time slot. This accumulation is repeated at the boundary of every segment window. Similarly, accumulation may be performed at the audio sink. Components within the audio sink may only read received data if status signals from all related sinks indicate that predefined thresholds have been reached. By providing such accumulation options, audio fidelity is maintained across multiple audio data channels.

    Abstract translation: 公开了多声道音频对准方案。 本公开的一个方面提供了音频源在多个相关音频通道上的累积。 相关的音频通道表示它们的相互关联性，当所有相关的音频通道都具有要发送的数据时，源将数据释放到串行低功率芯片间媒体总线（SLIMbus）的时隙上，使得相关的音频通道 在时隙的给定段窗口内。 在每个分段窗口的边界处重复该累积。 类似地，可以在音频接收器处执行累加。 音频接收器中的组件只能从所有相关接收器的状态信号指示已达到预定义的阈值时才读取接收到的数据。 通过提供这种累积选项，可以在多个音频数据通道之间保持音频保真度。

    MULTIPLE SLIMBUS CONTROLLERS FOR SLIMBUS COMPONENTS
    8.
    发明申请
    MULTIPLE SLIMBUS CONTROLLERS FOR SLIMBUS COMPONENTS 审中-公开
    SLIMBUS组件的多个SLIMBUS控制器

    公开(公告)号：WO2012149303A1

    公开(公告)日：2012-11-01

    申请号：PCT/US2012/035436

    申请日：2012-04-27

    Applicant: QUALCOMM INCORPORATED ,  GRUBER, Hans Georg ,  ARCEO, Julio ,  HARIHARAN, Magesh ,  MOHAN, Suren ,  LANDGUTH, Mark A.

    Inventor： GRUBER, Hans Georg ,  ARCEO, Julio ,  HARIHARAN, Magesh ,  MOHAN, Suren ,  LANDGUTH, Mark A.

    IPC: H04L12/46 ,  H04L12/66

    CPC classification number: H04L12/40013

    Abstract: Methods, systems, apparatuses, and computer-readable media for controlling components connected to and/or otherwise associated with a data bus are presented. According to one or more aspects of the disclosure, a plurality of processing devices having data bus management capability and at least one data bus associated with the plurality of processing devices may be identified. Subsequently, an inter-processor communication (IPC) layer for communication between the plurality of processing devices and the at least one data bus may be established over a messaging layer utilized by the at least one data bus. At least one component associated with the at least one data bus may then be controlled via the IPC layer using at least one of the plurality of processing devices.

    Abstract translation: 呈现用于控制连接到数据总线和/或以其他方式与数据总线相关的组件的方法，系统，装置和计算机可读介质。 根据本公开的一个或多个方面，可以识别具有数据总线管理能力的多个处理设备和与多个处理设备相关联的至少一个数据总线。 随后，可以通过由至少一个数据总线使用的消息传递层来建立用于在多个处理设备和至少一个数据总线之间通信的处理器间通信（IPC）层。 然后可以使用多个处理设备中的至少一个通过IPC层来控制与至少一个数据总线相关联的至少一个组件。

    DIRECT MEMORY SWAPPING BETWEEN NAND FLASH AND SRAM WITH ERROR CORRECTION CODING
    9.
    发明申请
    DIRECT MEMORY SWAPPING BETWEEN NAND FLASH AND SRAM WITH ERROR CORRECTION CODING 审中-公开
    NAND FLASH与具有错误校正编码的SRAM之间的直接存储器切换

    公开(公告)号：WO2003073259A1

    公开(公告)日：2003-09-04

    申请号：PCT/US2003/005316

    申请日：2003-02-21

    Applicant: QUALCOMM, INCORPORATED

    Inventor： WEI, Jian ,  KANG, Inyup ,  ARCEO, Julio ,  HUSSEINI, Jalal ,  LI, Tao ,  MEAGHER, Bruce ,  HIGGINS, Richard ,  OISHI, Moto ,  RODRIGUES, Brian

    IPC: G06F3/06

    CPC classification number: G11C7/1006 ,  G06F3/0601 ,  G06F11/1068 ,  G06F13/1684 ,  G06F2003/0692 ,  G11C11/005

    Abstract: Memory architectures and techniques that support direct memory swapping between NAND Flash and SRAM with error correction coding (ECC). In a specific design, a memory architecture includes a first storage unit (e.g., an SRAM) operative to provide storage of data, a second storage unit (e.g., a NAND Flash) operative to provide (mass) storage of data, an EMI unit implemented within an ASIC and operative to provide control signals for the storage units, and a data bus coupled to both storage units and the EMI unit. The two storage units are implemented external to the ASIC, and each storage unit is operable to store data from the other storage unit via the data bus when the other storage unit is being accessed by the EMI unit. The EMI unit may include an ECC unit operative to perform block coding of data transferred to/from the second storage unit.

    Abstract translation: 通过纠错编码（ECC）支持NAND Flash和SRAM之间的直接内存交换的内存架构和技术。 在具体设计中，存储器架构包括可操作以提供数据存储的第一存储单元（例如，SRAM），可操作地提供数据存储的第二存储单元（例如，NAND闪存），EMI单元 实现在ASIC内并且可操作以提供用于存储单元的控制信号，以及耦合到两个存储单元和EMI单元的数据总线。 两个存储单元在ASIC外部实现，并且当另一存储单元被EMI单元访问时，每个存储单元可操作以经由数据总线从另一个存储单元存储数据。 EMI单元可以包括ECC单元，其用于对从第二存储单元传送到/从第二存储单元的数据执行块编码。

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