公开(公告)号：WO2022271376A1

公开(公告)日：2022-12-29

申请号：PCT/US2022/030533

申请日：2022-05-23

Applicant: QUALCOMM INCORPORATED

Inventor： CHAVA, Bharani ,  ROY, Abinash ,  SONG, Stanley Seungchul ,  KIM, Jonghae

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/498 ,  H01L21/4857 ,  H01L2224/16227 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5385 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50

Abstract: A package comprising a substrate, a first integrated device coupled to the substrate, a second integrated device coupled to the substrate, a first bridge and a second bridge. The first bridge is coupled to the first integrated device and the second integrated device. The first bridge is configured to provide at least one first electrical path between the first integrated device and the second integrated device. The first bridge is coupled to a top portion of the first integrated device and a top portion of the second integrated device. The second bridge is coupled to the first integrated device and the second integrated device. The second bridge is configured to provide at least one second electrical path between the first integrated device and the second integrated device.

公开(公告)号：EP4214750A1

公开(公告)日：2023-07-26

申请号：EP21758907.6

申请日：2021-07-30

Applicant: QUALCOMM INCORPORATED

Inventor： SONG, Stanley Seungchul ,  SHARMA, Deepak ,  CHAVA, Bharani ,  LIM, Hyeokjin ,  FENG, Peijie ,  KANG, Seung Hyuk ,  KIM, Jonghae ,  CHIDAMBARAM, Periannan ,  RIM, Kern ,  NALLAPATI, Giridhar ,  BOYNAPALLI, Venugopal ,  VANG, Foua

IPC: H01L23/528 ,  H01L23/535 ,  H01L21/8238 ,  H01L23/48

公开(公告)号：WO2022164527A1

公开(公告)日：2022-08-04

申请号：PCT/US2021/063630

申请日：2021-12-15

Applicant: QUALCOMM INCORPORATED

Inventor： CHAVA, Bharani ,  ROY, Abinash

IPC: H01L23/50 ,  H01L23/538

Abstract: A package that includes a substrate and integrated device coupled to the substrate. The integrated device includes a first core and a second core. The substrate includes a first power interconnect configured to provide a first electrical path for a first power resource to the first core of the integrated device. The substrate includes a second power interconnect configured to provide a second electrical path for a second power resource to the second core of the integrated device. The substrate includes a switch coupled to the first power interconnect and the second power interconnect, where if the switch is turned on, the switch is configured to enable at least some of the power resource from the second power resource to contribute to the first core of the integrated device.

公开(公告)号：WO2022055598A1

公开(公告)日：2022-03-17

申请号：PCT/US2021/039621

申请日：2021-06-29

Applicant: QUALCOMM INCORPORATED

Inventor： CHAVA, Bharani ,  SONG, Stanley, Seungchul ,  ROY, Abinash ,  KIM, Jonghae

IPC: H01L25/16 ,  H01L25/065 ,  H01L23/528 ,  H01L21/98 ,  H01L25/18

Abstract: An integrated circuit (IC) package is described. The IC package includes a first die having a first power delivery network on the first die. The IC package also includes a second die having a second power delivery network on the second die. The first die is stacked on the second die. The IC package further includes package voltage regulators integrated with and coupled to the first die and/or the second die within a package core of the integrated circuit package.

公开(公告)号：WO2022125172A1

公开(公告)日：2022-06-16

申请号：PCT/US2021/052851

申请日：2021-09-30

Applicant: QUALCOMM INCORPORATED [US]/[US]

Inventor： SHAIK, Khaja, Ahmad ,  CHAVA, Bharani

IPC: G11C14/00 ,  G11C11/412

Abstract: An exemplary memory bit cell circuit, including a bit line coupled to an SRAM bit cell circuit and an NVM bit cell circuit, with reduced area and reduced power consumption, included in a memory bit cell array circuit, is disclosed. The SRAM bit cell circuit includes cross-coupled true and complement inverters and a first access circuit coupled to the bit line. The NVM bit cell circuit includes an NVM device coupled to the bit line by a second access circuit and is coupled to the SRAM bit cell circuit. Data stored in the SRAM bit cell circuit and the NVM bit cell circuit are accessed based on voltages on the bit line. A true SRAM data is determined by an SRAM read voltage on the bit line, and an NVM data in the NVM bit cell circuit is determined by a first NVM read voltage on the bit line.

公开(公告)号：WO2022109513A1

公开(公告)日：2022-05-27

申请号：PCT/US2021/071915

申请日：2021-10-18

Applicant: QUALCOMM INCORPORATED

Inventor： SONG, Stanley Seungchul ,  CHAVA, Bharani

IPC: H01L21/60 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H01L21/98

Abstract: Integrated circuit (IC) packages employing front side hack-end-of-line (FS-BEOL) to back side back-end-of-line (BS-BEOL) stacking for three-dimensional (3D) die stacking. To facilitate providing additional electrical routing paths for die-to-die interconnections between stacked IC dice in the IC package, a BS-BEOL metallization structure (202) of a first die (104(1)) of the stacked IC dice of the IC package is stacked adjacent to a FS-BEOL metallization structure (216) of a second die (104(2)) of the stacked IC dice. Electrical routing paths for die-to-die interconnections between the stacked IC dice are provided from the BS-BEOL metallization structure (202) of the first die to the FS-BEOL metallization structure (216) of the second die. It may be more feasible to form shorter electrical routing paths in the thinner BS-BEOL metallization structure than in a FS-BEOL metallization structure for lower-resistance and/or lower-capacitance die-to-die interconnections for faster and/or compatible performance of semiconductor devices in the IC dice.

公开(公告)号：WO2022093413A1

公开(公告)日：2022-05-05

申请号：PCT/US2021/050317

申请日：2021-09-14

Applicant: QUALCOMM INCORPORATED

Inventor： SHAIK, Khaja Ahmad ,  CHAVA, Bharani ,  PATHAN, Dawuth Shadulkhan

IPC: G06F7/523 ,  G06F7/544 ,  G11C11/41

Abstract: Low-power compute-in-memory (CIM) systems employing CIM circuits that include static random access memory (SRAM) bit cells circuits. The CIM circuits can be used for multiply-and-accumulate (MAC) operations. The CIM circuits can include five-transistor (5T) SRAM bit cells that each have a single bit line coupled to an access circuit for accessing the SRAM bit cell for read/write operations. The CIM circuit also includes a multiplication circuit (e.g., an exclusive OR (XOR)-based circuit) coupled to the SRAM bit cell. The CIM circuit is configured to perform multiplication of an input data value received by the multiplication circuit with a weight data value stored in the SRAM bit cell. The reduction of an access circuit in the 5T SRAM bit cell allows the pull-up voltage at a supply voltage rail coupled to the inverters of the 5T SRAM bit cell to be reduced to reduce standby power while providing storage stability.

公开(公告)号：WO2022051028A1

公开(公告)日：2022-03-10

申请号：PCT/US2021/041076

申请日：2021-07-09

Applicant: QUALCOMM INCORPORATED

Inventor： CHAVA, Bharani ,  SONG, Stanley Seungchul ,  SHARIFF, Mohammed Yousuff

IPC: H01L23/522 ,  H01L23/528

Abstract: Integrated circuits (ICs) employing front side (FS) back end-of-line (BEOL) (FS-BEOL) input/output (I/O) routing and back side (BS)) BEOL (BS-BEOL) power routing for current flow organization, and related IC packages and methods of fabricating are disclosed. The IC includes a FS-BEOL metallization structure disposed on a first side of a semiconductor layer and a BS-BEOL metallization structure disposed on a second side of the semiconductor layer. The FS-BEOL metallization structure is configured to route I/O signals to the semiconductor devices. The FS-BEOL metallization structure of the IC is also configured to receive power signals to be routed to the semiconductor devices. However, to avoid the need to route the power signals to semiconductor devices through the FS-BEOL metallization structure, thus increasing routing density and complexity the FS-BEOL metallization structure, the power signals are routed from the FS-BEOL metallization structure to the BS-BEOL metallization structure and to semiconductor devices for power.

公开(公告)号：EP4248488A1

公开(公告)日：2023-09-27

申请号：EP21810245.7

申请日：2021-10-18

Applicant: QUALCOMM INCORPORATED

Inventor： SONG, Stanley Seungchul ,  CHAVA, Bharani

IPC: H01L21/60 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H01L21/98

公开(公告)号：WO2022271409A1

公开(公告)日：2022-12-29

申请号：PCT/US2022/031340

申请日：2022-05-27

Applicant: QUALCOMM INCORPORATED

Inventor： ROY, Abinash ,  VEMULA, Lohith Kumar ,  CHAVA, Bharani ,  KIM, Jonghae

IPC: H01L23/13 ,  H01L23/498 ,  H01L23/50 ,  H01G4/232 ,  H01L21/4803 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/642 ,  H01L25/16

Abstract: A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects comprising a first interconnect and a second interconnect, a capacitor located at least partially in the substrate, the capacitor comprising a first terminal and a second terminal, a first solder interconnect coupled to a first side surface of the first terminal and the first interconnect, and a second solder interconnect coupled to a second side surface of the second terminal and the second interconnect.