公开(公告)号：WO2018194753A1

公开(公告)日：2018-10-25

申请号：PCT/US2018/019696

申请日：2018-02-26

Applicant: QUALCOMM INCORPORATED

Inventor： COUTTS, Ryan Michael ,  ZAYNOUN, Samy Shafik Tawfik ,  PENZES, Paul Ivan

IPC: G01R31/317 ,  G01R31/3193 ,  G06F11/07 ,  H03K5/04

Abstract: Various aspects of this disclosure describe measuring timing slack using an endpoint criticality sensor on a chip. A sensor circuit is attached to sensitive endpoints on the chip (e.g., logical gates in a timing critical path) so that the sensor circuit receives the endpoint's data signal and clock signal. The sensor circuit introduces skew between the data signal and the clock signal by delaying the data signal more than the clock signal, and compares skewed data signals to determine if an error occurs because of the induced skew. By delaying the data signal with different delay amounts and monitoring what delays cause errors, an amount of timing slack in the data signal and clock signal (e.g., margin to criticality) is measured during operation of the chip for relevant circuitry to the system implemented on the chip, compared to test circuitry operating while the chip is in a test mode.

公开(公告)号：WO2017044341A1

公开(公告)日：2017-03-16

申请号：PCT/US2016/049300

申请日：2016-08-29

Applicant: QUALCOMM INCORPORATED

Inventor： COUTTS, Ryan Michael ,  MITTAL, Rajat ,  SAEIDI, Mehdi ,  PENZES, Paul Ivan

IPC: G06F11/30

CPC classification number: G01K13/00 ,  G05B15/02 ,  G06F1/04 ,  G06F1/206 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  G06F11/3058 ,  G06F11/3093 ,  G06F2201/81

Abstract: In one embodiment, a temperature management system comprises a plurality of thermal sensors at different locations on a chip, and a temperature manager. The temperature manager is configured to receive a plurality of temperature readings from the thermal sensors, to fit a quadratic temperature model to the received temperature readings, and to estimate a hotspot temperature on the chip using the fitted quadratic temperature model.

Abstract translation: 在一个实施例中，温度管理系统包括在芯片上的不同位置处的多个热传感器和温度管理器。 温度管理器被配置为从热传感器接收多个温度读数，以将二次温度模型拟合到接收到的温度读数，并且使用拟合的二次温度模型来估计芯片上的热点温度。

公开(公告)号：WO2015109188A1

公开(公告)日：2015-07-23

申请号：PCT/US2015/011762

申请日：2015-01-16

Applicant: QUALCOMM INCORPORATED

Inventor： COUTTS, Ryan Michael

IPC: H03K19/00 ,  H03K19/003

CPC classification number: G05B13/0205 ,  G01R19/0084 ,  G01R21/006 ,  G01R27/2605 ,  H03K17/687 ,  H03K19/0016 ,  H03K19/00315 ,  Y10T307/76

Abstract: A method for powering up a circuit comprising a plurality of sections (310(1)-310(M)) of progressively increasing size is described. The method comprises receiving a signal for powering up the circuit, and in response to the signal, sequentially powering up the plurality of sections (310(1)-310(M)) in an order of increasing size.

Abstract translation: 描述了逐渐增加尺寸的包括多个部分（310（1）-310（M））的电路的上电方法。 该方法包括接收用于为电路供电的信号，并且响应于该信号，按照增大尺寸的顺序顺序上电多个部分（310（1）-310（M））。

公开(公告)号：EP3152636B1

公开(公告)日：2017-09-27

申请号：EP15726833.5

申请日：2015-05-18

Applicant: Qualcomm Incorporated

Inventor： COUTTS, Ryan Michael ,  PAL, Dipti Ranjan

IPC: G06F1/08 ,  G06F1/20 ,  G06F1/32

CPC classification number: G06F1/08 ,  G06F1/206 ,  G06F1/324 ,  H03K21/026 ,  H03K23/662 ,  H03L1/022 ,  Y02D10/126 ,  Y02D10/16

Abstract: Systems and methods for controlling a frequency of a clock signal by selectively swallowing pulses in the clock signal are described herein. In one embodiment, a method for adjusting a frequency of a clock signal comprises receiving the clock signal, and swallowing pulses in the clock signal according to a repeating clock-swallowing pattern, wherein the pattern is defined by a sequence of numbers.

Abstract translation: 本文描述了通过选择性地吞服时钟信号中的脉冲来控制时钟信号的频率的系统和方法。 在一个实施例中，一种用于调整时钟信号的频率的方法包括：接收时钟信号;以及根据重复的时钟吞咽模式吞服时钟信号中的脉冲，其中该模式由一系列数字限定。

公开(公告)号：EP3095053B1

公开(公告)日：2019-07-24

申请号：EP15702071.0

申请日：2015-01-15

Applicant: Qualcomm Incorporated

Inventor： COUTTS, Ryan Michael

IPC: G06F17/50 ,  G01R31/28 ,  G11C5/14 ,  G01R27/26

公开(公告)号：WO2019022825A2

公开(公告)日：2019-01-31

申请号：PCT/US2018/033975

申请日：2018-05-22

Applicant: QUALCOMM INCORPORATED

Inventor： COUTTS, Ryan Michael ,  SOLKI, Shahin ,  PENZES, Paul Ivan

IPC: H03K5/19

Abstract: An integrated circuit is disclosed for voltage histogram generation. In an example aspect, the integrated circuit includes multiple delay stages coupled in series and multiple counters. The multiple delay stages include a first signaling path to propagate a first signal at a first propagation speed and a second signaling path to propagate a second signal at a second propagation speed. The first propagation speed is slower than the second propagation speed, and both speeds are voltage-dependent. The multiple delay stages also include a respective time-of-arrival (TOA) detection circuit for each respective delay stage. The respective TOA detection circuit generates a respective stage timing signal indicative of a relative arrival time between the first and second signals at the respective delay stage. The multiple counters are respectively coupled to the multiple delay stages and have respective counter values. The respective counter values are incremented responsive to the respective stage timing signal.

公开(公告)号：WO2015191250A1

公开(公告)日：2015-12-17

申请号：PCT/US2015/031428

申请日：2015-05-18

Applicant: QUALCOMM INCORPORATED

Inventor： COUTTS, Ryan Michael ,  PAL, Dipti Ranjan

IPC: G06F1/08 ,  G06F1/20 ,  G06F1/32

CPC classification number: G06F1/08 ,  G06F1/206 ,  G06F1/324 ,  H03K21/026 ,  H03K23/662 ,  H03L1/022 ,  Y02D10/126 ,  Y02D10/16

Abstract: Systems and methods for controlling a frequency of a clock signal by selectively swallowing pulses in the clock signal are described herein. In one embodiment, a method for adjusting a frequency of a clock signal comprises receiving the clock signal, and swallowing pulses in the clock signal according to a repeating clock-swallowing pattern, wherein the pattern is defined by a sequence of numbers.

Abstract translation: 这里描述了通过选择性地吞咽时钟信号中的脉冲来控制时钟信号的频率的系统和方法。 在一个实施例中，一种用于调整时钟信号的频率的方法包括：根据重复的时钟吞咽模式接收时钟信号和吞咽时钟信号中的脉冲，其中，所述模式由数字序列定义。

公开(公告)号：WO2015160454A1

公开(公告)日：2015-10-22

申请号：PCT/US2015/020539

申请日：2015-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： COUTTS, Ryan Michael ,  POPOVICH, Mikhail

IPC: G06F1/26

CPC classification number: H03K17/16 ,  G06F1/26 ,  G06F1/28 ,  H02J7/0063 ,  H02J9/061 ,  H03K17/145 ,  H03K19/0175 ,  H03K19/20

Abstract: Aspects of an integrated circuit are disclosed. The integrated circuit includes a first circuit configured to be powered by a first voltage source, a second circuit configured to be powered by a second voltage source, a decoupling capacitor, and a controller configured to switch the decoupling capacitor between the first and second voltage source.

Abstract translation: 公开了集成电路的方面。 集成电路包括被配置为由第一电压源供电的第一电路，被配置为由第二电压源供电的第二电路，去耦电容器和被配置为在第一和第二电压源之间切换去耦电容器的控制器 。

公开(公告)号：WO2019022825A3

公开(公告)日：2019-01-31

申请号：PCT/US2018/033975

申请日：2018-05-22

Applicant: QUALCOMM INCORPORATED

Inventor： COUTTS, Ryan Michael ,  SOLKI, Shahin ,  PENZES, Paul Ivan

IPC: H03K5/19

Abstract: An integrated circuit is disclosed for voltage histogram generation. In an example aspect, the integrated circuit includes multiple delay stages coupled in series and multiple counters. The multiple delay stages include a first signaling path to propagate a first signal at a first propagation speed and a second signaling path to propagate a second signal at a second propagation speed. The first propagation speed is slower than the second propagation speed, and both speeds are voltage-dependent. The multiple delay stages also include a respective time-of-arrival (TOA) detection circuit for each respective delay stage. The respective TOA detection circuit generates a respective stage timing signal indicative of a relative arrival time between the first and second signals at the respective delay stage. The multiple counters are respectively coupled to the multiple delay stages and have respective counter values. The respective counter values are incremented responsive to the respective stage timing signal.

公开(公告)号：WO2016039857A1

公开(公告)日：2016-03-17

申请号：PCT/US2015/041394

申请日：2015-07-21

Applicant: QUALCOMM INCORPORATED

Inventor： COUTTS, Ryan Michael ,  WAI KIT, Siu ,  PENZES, Paul Ivan

IPC: H03K19/00

CPC classification number: H03K3/012 ,  G05B19/045 ,  H03K3/0372 ,  H03K17/223 ,  H03K19/0008

Abstract: Circuits and methods for reducing leakage are provided. In one example, a system (100) includes circuitry to reset a particular logic circuit (110a-110e, 120a-120d) to a state of reduced leakage. The state of reduced leakage would be known beforehand for the logic circuit. In this example, the logic circuit (110a-110e, 120a-120d) includes the combinational logic (120a-120d) as well as flip flops (110a-110e) that output a state to the combinational logic. Some of the flip flops are "SET" flip flops (assuming a 1 output value when a reset input is asserted) and some of the flip flops are "RESET" flip flops (assuming a 0 value when a reset input is asserted). The flip flops are chosen as inputs to the combinational logic so that the particular combination of zeros and ones output to the combinational logic puts the logic circuit in a state that is correlated with a desired level of leakage.

Abstract translation: 提供了减少泄漏的电路和方法。 在一个示例中，系统（100）包括将特定逻辑电路（110a-110e，120a-120d）复位到减少泄漏的状态的电路。 对于逻辑电路，预先知道减少泄漏的状态。 在该示例中，逻辑电路（110a-110e，120a-120d）包括组合逻辑（120a-120d）以及将状态输出到组合逻辑的触发器（110a-110e）。 一些触发器是“SET”触发器（当复位输入被置位时，假定为1个输出值），并且一些触发器是“RESET”触发器（假设复位输入被置位时为0）。 触发器被选择为组合逻辑的输入，使得零和一个输出到组合逻辑的特定组合将逻辑电路置于与期望的泄漏水平相关联的状态。