公开(公告)号：EP3219003A1

公开(公告)日：2017-09-20

申请号：EP15797796.8

申请日：2015-11-12

Applicant: Qualcomm Incorporated

Inventor： SOLKI, Shahin ,  MAHMOUDI, Farsheed

IPC: H02M3/157 ,  G06F1/26 ,  H02M3/158 ,  H02M1/00

CPC classification number: G06F1/26 ,  G06F1/3296 ,  H02M3/157 ,  H02M3/1588 ,  H02M2001/0025 ,  Y02B70/1466

Abstract: An apparatus and method are disclosed for providing voltage control at a load of a buck converter. The buck converter is in a feedback loop so that a reference voltage determines a pulse width modulated (PWM) signal that is fed to the buck converter, and an output voltage of the buck converter is fed back to a PWM control circuit to maintain a value of the output voltage. The load at the buck converter provides event counters to a transient load current prediction circuit, which uses a curve fitting algorithm or other adaptive control algorithm to predict a change in current at the load. The transient load current prediction circuit then manipulates the reference voltage in accordance with the predicted change in current at the load.

Abstract translation: 公开了一种用于在降压转换器的负载处提供电压控制的设备和方法。 降压转换器处于反馈回路中，使得参考电压确定被馈送到降压转换器的脉宽调制（PWM）信号，并且降压转换器的输出电压被反馈到PWM控制电路以保持值 的输出电压。 降压转换器的负载向瞬态负载电流预测电路提供事件计数器，该电路使用曲线拟合算法或其他自适应控制算法来预测负载电流的变化。 瞬态负载电流预测电路然后根据负载处的电流的预测变化来操纵参考电压。

公开(公告)号：WO2019022825A2

公开(公告)日：2019-01-31

申请号：PCT/US2018/033975

申请日：2018-05-22

Applicant: QUALCOMM INCORPORATED

Inventor： COUTTS, Ryan Michael ,  SOLKI, Shahin ,  PENZES, Paul Ivan

IPC: H03K5/19

Abstract: An integrated circuit is disclosed for voltage histogram generation. In an example aspect, the integrated circuit includes multiple delay stages coupled in series and multiple counters. The multiple delay stages include a first signaling path to propagate a first signal at a first propagation speed and a second signaling path to propagate a second signal at a second propagation speed. The first propagation speed is slower than the second propagation speed, and both speeds are voltage-dependent. The multiple delay stages also include a respective time-of-arrival (TOA) detection circuit for each respective delay stage. The respective TOA detection circuit generates a respective stage timing signal indicative of a relative arrival time between the first and second signals at the respective delay stage. The multiple counters are respectively coupled to the multiple delay stages and have respective counter values. The respective counter values are incremented responsive to the respective stage timing signal.

公开(公告)号：WO2016077642A1

公开(公告)日：2016-05-19

申请号：PCT/US2015/060471

申请日：2015-11-12

Applicant: QUALCOMM INCORPORATED

Inventor： SOLKI, Shahin ,  MAHMOUDI, Farsheed

IPC: H02M3/157 ,  G06F1/26 ,  H02M3/158 ,  H02M1/00

CPC classification number: G06F1/26 ,  G06F1/3296 ,  H02M3/157 ,  H02M3/1588 ,  H02M2001/0025 ,  Y02B70/1466

Abstract: An apparatus and method are disclosed for providing voltage control at a load of a buck converter. The buck converter is in a feedback loop so that a reference voltage determines a pulse width modulated (PWM) signal that is fed to the buck converter, and an output voltage of the buck converter is fed back to a PWM control circuit to maintain a value of the output voltage. The load at the buck converter provides event counters to a transient load current prediction circuit, which uses a curve fitting algorithm or other adaptive control algorithm to predict a change in current at the load. The transient load current prediction circuit then manipulates the reference voltage in accordance with the predicted change in current at the load.

Abstract translation: 公开了一种用于在降压转换器的负载处提供电压控制的装置和方法。 降压转换器处于反馈回路中，使得参考电压确定馈送到降压转换器的脉宽调制（PWM）信号，并且降压转换器的输出电压被反馈到PWM控制电路以维持值 的输出电压。 降压转换器的负载为瞬态负载电流预测电路提供事件计数器，该电路使用曲线拟合算法或其他自适应控制算法来预测负载电流的变化。 然后，瞬态负载电流预测电路根据预测的负载电流变化来操纵参考电压。

公开(公告)号：WO2019022825A3

公开(公告)日：2019-01-31

申请号：PCT/US2018/033975

申请日：2018-05-22

Applicant: QUALCOMM INCORPORATED

Inventor： COUTTS, Ryan Michael ,  SOLKI, Shahin ,  PENZES, Paul Ivan

IPC: H03K5/19

Abstract: An integrated circuit is disclosed for voltage histogram generation. In an example aspect, the integrated circuit includes multiple delay stages coupled in series and multiple counters. The multiple delay stages include a first signaling path to propagate a first signal at a first propagation speed and a second signaling path to propagate a second signal at a second propagation speed. The first propagation speed is slower than the second propagation speed, and both speeds are voltage-dependent. The multiple delay stages also include a respective time-of-arrival (TOA) detection circuit for each respective delay stage. The respective TOA detection circuit generates a respective stage timing signal indicative of a relative arrival time between the first and second signals at the respective delay stage. The multiple counters are respectively coupled to the multiple delay stages and have respective counter values. The respective counter values are incremented responsive to the respective stage timing signal.

公开(公告)号：WO2016137600A1

公开(公告)日：2016-09-01

申请号：PCT/US2016/013681

申请日：2016-01-15

Applicant: QUALCOMM INCORPORATED

Inventor： SOLKI, Shahin ,  PAL, Dipti Ranjan ,  PENZES, Paul Ivan

IPC: H03K5/156

CPC classification number: H03K5/1565 ,  H03K5/1504

Abstract: A duty cycle adjustment apparatus (200) includes a duty cycle adjustment determination module (204) configured to determine an adjustment to a duty cycle of a clock signal (203), and includes a clock delay module (232, 240) configured to receive the clock signal (203), to delay the clock signal through first (232) and second (240) delay stage modules (with a first (212,... 216) and a second (242,... 246) plurality of delay paths, respectively) based on the duty cycle adjustment determined by the duty cycle adjustment determination module (204), and to output the delayed clock signal (264). The second plurality of delay paths (242,... 246) have a greater delay difference between each of the corresponding delay paths than the first plurality of delay paths (212,... 216). The apparatus (200) further includes a duty cycle adjustment module (282) configured to receive the clock signal (203) and the delayed clock signal (264), to adjust the duty cycle of the clock signal based on the delayed clock signal, and to output a duty cycle adjusted clock signal (286).

Abstract translation: 占空比调整装置（200）包括：占空比调整确定模块（204），被配置为确定对时钟信号（203）的占空比的调整，并且包括时钟延迟模块（232,240），其被配置为接收 时钟信号（203），以延迟通过第一（232）和第二（240）延迟级模块的时钟信号（具有第一（212，... 216）和第二（242，... 246）多个延迟 路径），并且输出延迟的时钟信号（264）。 第二多个延迟路径（242，... 246）在每个相应的延迟路径之间具有比第一多个延迟路径（212，... 216）更大的延迟差。 装置（200）还包括配置成接收时钟信号（203）和延迟的时钟信号（264）的占空比调整模块（282），以基于延迟的时钟信号调整时钟信号的占空比，以及 以输出占空比调整时钟信号（286）。