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    SUBSTRATE COMPRISING ACOUSTIC RESONATORS CONFIGURED AS AT LEAST ONE ACOUSTIC FILTER
    4.
    发明申请
    SUBSTRATE COMPRISING ACOUSTIC RESONATORS CONFIGURED AS AT LEAST ONE ACOUSTIC FILTER 审中-公开

    公开(公告)号：WO2022047206A1

    公开(公告)日：2022-03-03

    申请号：PCT/US2021/048024

    申请日：2021-08-27

    Applicant: QUALCOMM INCORPORATED

    Inventor： KIM, Jonghae ,  LAN, Je-Hsiung ,  DUTTA, Ranadeep

    IPC: H03H9/05 ,  H03H9/10 ,  H03H9/60 ,  H03H3/02 ,  H03H9/02 ,  H03H9/56 ,  H03H9/64 ,  H03H3/007

    Abstract: A substrate (202) that includes an encapsulation layer (203), a first acoustic resonator (205), a second acoustic resonator (207), at least one first dielectric layer (240), a plurality of first interconnects (244), at least one second dielectric layer (260), and a plurality of second interconnects (264). The first acoustic resonator is located in the encapsulation layer. The first acoustic resonator includes a first piezoelectric substrate (250) comprising a first thickness. The second acoustic resonator (207) is located in the encapsulation layer. The second acoustic resonator includes a second piezoelectric substrate (270) comprising a second thickness that is different than the first thickness. The at least one first dielectric layer is coupled to a first surface of the encapsulation layer. The plurality of first interconnects is coupled to the first surface of the encapsulation layer. The plurality of first interconnects is located at least in the at least one first dielectric layer.

    COMPOUND SEMICONDUCTOR AND COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) TRANSISTOR INTEGRATION
    5.
    发明申请
    COMPOUND SEMICONDUCTOR AND COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) TRANSISTOR INTEGRATION 审中-公开

    公开(公告)号：WO2022197390A1

    公开(公告)日：2022-09-22

    申请号：PCT/US2022/015673

    申请日：2022-02-08

    Applicant: QUALCOMM INCORPORATED

    Inventor： DUTTA, Ranadeep ,  KIM, Jonghae ,  LAN, Je-Hsiung

    IPC: H01L21/8258 ,  H01L27/085 ,  H01L21/02

    Abstract: A radio frequency integrated circuit (RFIC) includes a bulk semiconductor substrate (402). The RFIC also includes a compound semiconductor field effect transistor (FET, 420). The compound semiconductor FET is composed of a gallium nitride (GaN) epitaxial stack (430) in a trench (404) in the bulk semiconductor substrate having sidewall spacers (406, 408). The sidewall spacers are between the GaN epitaxial stack and sidewalls of the trench. A carbonized surface layer (440) is at a base of the trench and coupled to the GaN epitaxial stack. The RFIC further includes a complementary metal oxide semiconductor (CMOS, 410) transistor integrated with the compound semiconductor FET (420) on the bulk semiconductor substrate (402).

    INTEGRATED DEVICE WITH ELECTROMAGNETIC SHIELD
    6.
    发明申请
    INTEGRATED DEVICE WITH ELECTROMAGNETIC SHIELD 审中-公开

    公开(公告)号：WO2021112979A1

    公开(公告)日：2021-06-10

    申请号：PCT/US2020/057830

    申请日：2020-10-29

    Applicant: QUALCOMM INCORPORATED

    Inventor： KIM, Jonghae ,  LAN, Je-Hsiung ,  DUTTA, Ranadeep

    IPC: H01L23/552 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L23/538

    Abstract: Improve EM coupling for the wafer-bonding process from a first wafer to a second wafer by a shielding technique. Examples may include building an EM shield implemented by BEOL-stacks/routings, bonding contacts, and TSVs for a closed-loop shielding platform for the integrated device to minimize EM interference from active devices due to eddy currents. The shield may be implemented in the active device layer during a wafer-to-wafer bonding-process that uses two different device layers/wafers, an active device layer/wafer and a passive device layer/wafer. The shield may be designed by the patterned routings for both I/O ports and the GND contacts.

    THREE TERMINAL SEMICONDUCTOR DEVICE WITH VARIABLE CAPACITANCE
    10.
    发明公开
    THREE TERMINAL SEMICONDUCTOR DEVICE WITH VARIABLE CAPACITANCE 审中-公开
    脱脂奶酪蛋白酱

    公开(公告)号：EP2959513A1

    公开(公告)日：2015-12-30

    申请号：EP14707587.3

    申请日：2014-02-17

    Applicant: Qualcomm Incorporated

    Inventor： DUTTA, Ranadeep

    IPC: H01L29/66 ,  H01L27/08 ,  H01L29/93 ,  H01L29/94

    CPC classification number: H01L29/93 ,  H01L27/0808 ,  H01L29/66174 ,  H01L29/66181 ,  H01L29/945

    Abstract: Methods and apparatus for implementing variable, e.g., tunable, 3 terminal capacitance devices are described. In various embodiments vertical control pillars spaced apart from one another extend in a well having an opposite polarity than the polarity of the control pillars. The control pillars are arranged in a line that extends parallel to but between a deep trench gate and a well pickup. By varying the voltage applied to the control pillars the size of the depletion zone around the pillars can be varied resulting in a change in capacitance between the trench gate and pickup terminal connected to the well pickup. The generally vertical nature of the control pillars facilities control over a wide range of voltages while allowing for manufacturing using common semiconductor manufacturing steps making the device easy to implement on a chip with other semiconductor devices.

    Abstract translation: 描述用于实现变量例如可调谐的3端子电容器件的方法和装置。 在各种实施例中，彼此间隔开的垂直控制柱在具有与控制柱的极性相反的极性的井中延伸。 控制柱布置成平行于深沟槽栅极和阱拾取器之间延伸的线。 通过改变施加到控制柱的电压，可以改变柱周围的耗尽区的尺寸，导致沟槽栅极和连接到阱拾取器的拾取端之间的电容变化。 控制柱设施的大体上垂直的特性控制在宽范围的电压，同时允许使用通常的半导体制造步骤进行制造，使得器件易于与其他半导体器件在芯片上实现。

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