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    REDUCED SUSCEPTIBILITY TO ELECTROSTATIC DISCHARGE DURING 3D SEMICONDUCTOR DEVICE BONDING AND ASSEMBLY
    1.
    发明申请
    REDUCED SUSCEPTIBILITY TO ELECTROSTATIC DISCHARGE DURING 3D SEMICONDUCTOR DEVICE BONDING AND ASSEMBLY 审中-公开
    三维半导体器件接合和​​组装过程中降低静电放电的可能性

    公开(公告)号：WO2010118350A1

    公开(公告)日：2010-10-14

    申请号：PCT/US2010/030577

    申请日：2010-04-09

    Applicant: QUALCOMM INCORPORATED ,  HENDERSON, Brian M. ,  JALILIZEINALI, Reza ,  GU, Shiqun

    Inventor： HENDERSON, Brian M. ,  JALILIZEINALI, Reza ,  GU, Shiqun

    IPC: H01L21/98 ,  H01L23/60 ,  H01L25/065 ,  H01L21/00

    CPC classification number: H01L23/488 ,  H01L21/50 ,  H01L21/67092 ,  H01L23/60 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16 ,  H01L2225/06513

    Abstract: A method to reduce electrostatic discharge susceptibility when assembling a stacked IC device. The method includes coupling a ground plane of a first semiconductor device (210/310/410/510) and a ground plane of a second semiconductor device (240/340/440/540 ) to substantially a same electrical potential. Active circuitry on the first semiconductor device and active circuitry on the second semiconductor device are electrically coupled after the ground planes are coupled. Electrically coupling the ground planes of the first and the second semiconductor device creates a preferred electrostatic discharge path to ground, thus minimizing potential damage to sensitive circuit elements.

    Abstract translation: 一种组装堆叠IC器件时降低静电放电敏感性的方法。 该方法包括将第一半导体器件（210/310/410/510）的接地平面和第二半导体器件（240/340/440/540）的接地平面耦合到基本相同的电位。 第一半导体器件上的有源电路和第二半导体器件上的有源电路在接地平面耦合之后被电耦合。 电耦合第一和第二半导体器件的接地平面产生优选的接地静电放电路径，从而最小化对敏感电路元件的潜在损害。

    ELECTROSTATIC PROTECTION FOR STACKED MULTI-CHIP INTEGRATED CIRCUITS
    3.
    发明申请
    ELECTROSTATIC PROTECTION FOR STACKED MULTI-CHIP INTEGRATED CIRCUITS 审中-公开
    用于堆叠多芯片集成电路的静电保护

    公开(公告)号：WO2014055777A1

    公开(公告)日：2014-04-10

    申请号：PCT/US2013/063297

    申请日：2013-10-03

    Applicant: QUALCOMM INCORPORATED

    Inventor： HENDERSON, Brian M. ,  TAN, Chiew-Guan ,  UVIEGHARA, Gregory A. ,  JALILIZEINALI, Reza

    IPC: H01L23/60 ,  H01L23/525 ,  H01L25/065 ,  H01L25/00

    CPC classification number: H01L23/5256 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/60 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/73257 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014

    Abstract: One feature pertains to a multi-chip module that comprises at least a first integrated circuit (IC) die and a second IC die. The second IC die has an input/output (I/O) node electrically coupled to the first IC die by a through substrate via. The second dies active surface also includes a fuse that is electrically coupled to the I/O node and adapted to protect the second IC die from damage caused by an electrostatic discharge (ESD). In particular, the fuse protects the second IC die from ESD that may be generated as a result of electrically coupling the first die to the second die during the manufacturing of the multi-chip module. Upon coupling the first die to the second die, the fuse may bypass the ESD current generated by the ESD to ground. After packaging of the multi-chip module is complete, the fuse may be blown open.

    Abstract translation: 一个特征涉及包括至少第一集成电路（IC）管芯和第二IC管芯的多芯片模块。 第二IC芯片具有通过基板通孔电耦合到第一IC裸片的输入/输出（I / O）节点。 第二裸片有源表面还包括电连接到I / O节点并且适于保护第二IC裸片免受静电放电（ESD）引起的损坏的熔丝。 特别地，保险丝保护第二IC芯片免受由于在多芯片模块的制造期间将第一裸片电耦合到第二裸片而产生的ESD。 在将第一管芯耦合到第二管芯时，熔丝可以将由ESD产生的ESD电流旁路到地。 多芯片模块封装完成后，保险丝可能会断开。

    ELECTROSTATIC PROTECTION FOR STACKED MULTI-CHIP INTEGRATED CIRCUITS
    8.
    发明公开
    ELECTROSTATIC PROTECTION FOR STACKED MULTI-CHIP INTEGRATED CIRCUITS 审中-公开
    ELEKTROSTATISCHER SCHUTZFÜRGESTAPELTE INTEGRIERTE SCHALTUNGEN MIT MEHREREN CHIPS

    公开(公告)号：EP2904638A1

    公开(公告)日：2015-08-12

    申请号：EP13779997.9

    申请日：2013-10-03

    Applicant: Qualcomm Incorporated

    Inventor： HENDERSON, Brian M. ,  TAN, Chiew-Guan ,  UVIEGHARA, Gregory A. ,  JALILIZEINALI, Reza

    IPC: H01L23/60 ,  H01L23/525 ,  H01L25/065 ,  H01L25/00

    Abstract: One feature pertains to a multi-chip module that comprises at least a first integrated circuit (IC) die and a second IC die. The second IC die has an input/output (I/O) node electrically coupled to the first IC die by a through substrate via. The second die's active surface also includes a fuse that is electrically coupled to the I/O node and adapted to protect the second IC die from damage caused by an electrostatic discharge (ESD). In particular, the fuse protects the second IC die from ESD that may be generated as a result of electrically coupling the first die to the second die during the manufacturing of the multi-chip module. Upon coupling the first die to the second die, the fuse may bypass the ESD current generated by the ESD to ground. After packaging of the multi-chip module is complete, the fuse may be blown open.

    Abstract translation: 一个特征涉及至少包括第一集成电路（IC）管芯和第二IC管芯的多芯片模块。 第二IC芯片具有通过基板通孔电耦合到第一IC裸片的输入/输出（I / O）节点。 第二管芯的有源表面还包括电耦合到I / O节点并且适于保护第二IC管芯免受静电放电（ESD）引起的损坏的熔丝。 特别地，保险丝保护第二IC芯片免受可能由于在制造多芯片模块期间将第一裸片电耦合到第二裸片而产生的ESD。 在将第一管芯耦合到第二管芯时，熔丝可以将由ESD产生的ESD电流旁路到地。 多芯片模块封装完成后，保险丝可能会断开。

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