公开(公告)号：WO2013106583A1

公开(公告)日：2013-07-18

申请号：PCT/US2013/021050

申请日：2013-01-10

Applicant: QUALCOMM Incorporated

Inventor： PLONDKE, Erich, James ,  INGLE, Ajay, Anant ,  CODRESCU, Lucian

IPC: G06F12/10 ,  G06F9/30 ,  G06F12/08

CPC classification number: G06F12/0811 ,  G06F12/0888 ,  G06F12/1027

Abstract: Systems and methods for performing non-allocating memory access instructions with physical address. A system includes a processor, one or more levels of caches, a memory, a translation look-aside buffer (TLB), and a memory access instruction specifying a memory access by the processor and an associated physical address. Execution logic is configured to bypass the TLB for the memory access instruction and perform the memory access with the physical address, while avoiding allocation of one or more intermediate levels of caches where a miss may be encountered.

Abstract translation: 用于执行具有物理地址的非分配存储器访问指令的系统和方法。 系统包括处理器，一个或多个级别的高速缓存，存储器，翻译后备缓冲器（TLB）以及指定处理器的存储器访问和相关联的物理地址的存储器访问指令。 执行逻辑被配置为绕过用于存储器访问指令的TLB并且使用物理地址执行存储器访问，同时避免分配可能遇到未命中的一个或多个中间级别的高速缓存。

公开(公告)号：WO2014150636A1

公开(公告)日：2014-09-25

申请号：PCT/US2014/023849

申请日：2014-03-12

Applicant: QUALCOMM INCORPORATED

Inventor： INGLE, Ajay, Anant ,  HOYLE, David, J. ,  HOFFMAN, Marc, M.

IPC: G06F9/30

CPC classification number: G06F15/8053 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109

Abstract: An example method for placing one or more element data values into an output vector includes identifying a vertical permute control vector including a plurality of elements, each element of the plurality of elements including a register address. The method also includes for each element of the plurality of elements, reading a register address from the vertical permute control vector. The method further includes retrieving a plurality of element data values based on the register address. The method also includes identifying a horizontal permute control vector including a set of addresses corresponding to an output vector. The method further includes placing at least some of the retrieved element data values of the plurality of element data values into the output vector based on the set of addresses in the horizontal permute control vector.

Abstract translation: 将一个或多个元素数据值放置在输出向量中的示例性方法包括识别包括多个元素的垂直置换控制向量，所述多个元素中的每个元素包括寄存器地址。 该方法还包括对于多个元件的每个元件，从垂直置换控制向量读取寄存器地址。 该方法还包括基于寄存器地址检索多个元素数据值。 该方法还包括识别包括对应于输出向量的一组地址的水平置换控制向量。 该方法还包括基于水平置换控制向量中的地址集合将至少一些所检索到的多个元素数据值的元素数据值放入输出向量中。

公开(公告)号：WO2010102134A1

公开(公告)日：2010-09-10

申请号：PCT/US2010/026249

申请日：2010-03-04

Applicant: QUALCOMM INCORPORATED ,  BASSETT, Paul, Douglas ,  INGLE, Ajay, Anant ,  JAMIL, Sujat ,  CODRESCU, Lucian ,  AHMED, Muhammad

Inventor： BASSETT, Paul, Douglas ,  INGLE, Ajay, Anant ,  JAMIL, Sujat ,  CODRESCU, Lucian ,  AHMED, Muhammad

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F2212/1016 ,  G06F2212/652 ,  G06F2212/654 ,  G06F2212/655

Abstract: An apparatus and method to translate virtual addresses to physical addresses in a base plus offset addressing mode are disclosed. In an embodiment, a method includes performing a first translation lookaside buffer (TLB) lookup based on a base address value to retrieve a speculative physical address. While performing the TLB lookup based on the base address value, the base address value is added to an offset value to generate an effective address value. The method also includes performing a comparison of the base address value and the effective address value based on a variable page size to determine whether the speculative physical address corresponds to the effective address.

Abstract translation: 公开了一种将虚拟地址转换为基本加偏移寻址模式的物理地址的装置和方法。 在一个实施例中，一种方法包括基于基地址值执行第一翻译后备缓冲器（TLB）查找以检索推测性物理地址。 在基于基地址值执行TLB查找的同时，将基地址值添加到偏移值以生成有效的地址值。 该方法还包括基于可变页大小执行基地址值与有效地址值的比较，以确定推测物理地址是否对应于有效地址。

公开(公告)号：WO2009158269A1

公开(公告)日：2009-12-30

申请号：PCT/US2009/047795

申请日：2009-06-18

Applicant: QUALCOMM INCORPORATED ,  INGLE, Ajay, Anant ,  KOOB, Christopher, Edward

Inventor： INGLE, Ajay, Anant ,  KOOB, Christopher, Edward

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  Y02D10/13

Abstract: A memory management unit (MMU) for servicing transaction requests from one or more processor threads is described. The MMU can include a translation lookaside buffer (TLB). The TLB can include a storage module and a logic circuit. The storage module can store a bit indicating one of a plurality of interfaces. The bit can be associated with a physical address range. The logic circuit can route a physical address within the physical address range to the one of the plurality of interfaces.

Abstract translation: 描述了用于维护来自一个或多个处理器线程的事务请求的存储器管理单元（MMU）。 MMU可以包括翻译后备缓冲器（TLB）。 TLB可以包括存储模块和逻辑电路。 存储模块可以存储指示多个接口之一的位。 该位可以与物理地址范围相关联。 逻辑电路可以将物理地址范围内的物理地址路由到多个接口之一。

公开(公告)号：WO2014133895A2

公开(公告)日：2014-09-04

申请号：PCT/US2014/017713

申请日：2014-02-21

Applicant: QUALCOMM INCORPORATED

Inventor： INGLE, Ajay, Anant ,  HOFFMAN, Marc, M. ,  FRIDMAN, Jose ,  CODRESCU, Lucian

IPC: G06F9/30

CPC classification number: G06F9/30105 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30163 ,  G06F9/345 ,  G06F9/3885

Abstract: Techniques are provided for executing a vector alignment instruction. A scalar register file in a first processor is configured to share one or more register values with a second processor, the one or more register values accessed from the scalar register file according to an Rt address specified in a vector alignment instruction, wherein a start location is determined from one of the shared register values. An alignment circuit in the second processor is configured to align data identified between the start location within a beginning Vu register of a vector register file (VRF) and an end location of a last Vu register of the VRF according to the vector alignment instruction. A store circuit is configured to select the aligned data from the alignment circuit and store the aligned data in the vector register file according to an alignment store address specified by the vector alignment instruction.

Abstract translation: 提供了用于执行向量对齐指令的技术。 第一处理器中的标量寄存器文件被配置为与第二处理器共享一个或多个寄存器值，所述一个或多个寄存器值根据矢量对准指令中指定的Rt地址从标量寄存器文件访问，其中开始位置 从共享寄存器值之一确定。 第二处理器中的对准电路被配置为根据向量对准指令将矢量寄存器文件（VRF）的起始Vu寄存器内的起始位置与VRF的最后一个Vu寄存器的结束位置之间标识的数据进行对准。 存储电路被配置为从对准电路中选择对准的数据，并根据由向量对准指令指定的对准存储地址将对准的数据存储在向量寄存器文件中。

公开(公告)号：WO2013059510A2

公开(公告)日：2013-04-25

申请号：PCT/US2012/060897

申请日：2012-10-18

Applicant: QUALCOMM INCORPORATED

Inventor： INGLE, Ajay, Anant ,  ZENG, Mao

IPC: G06F7/24 ,  G06F7/36 ,  G06F9/30

CPC classification number: G06F7/492 ,  G06F7/24 ,  G06F7/36 ,  G06F9/30 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/30036

Abstract: A method includes executing an instruction at a processor, where executing the instruction includes comparing a data value of a plurality of data values to a first element stored at a first location of a storage device. When the data value satisfies a condition with respect to the first element, the method includes moving the first element to a second location of the storage device and inserting the data value into the first location of the storage device.

Abstract translation: 一种方法包括在处理器处执行指令，其中执行指令包括将多个数据值的数据值与存储在存储设备的第一位置处的第一元素进行比较。 当数据值满足关于第一元素的条件时，该方法包括将第一元素移动到存储设备的第二位置，并将数据值插入存储设备的第一位置。

公开(公告)号：EP2972792A1

公开(公告)日：2016-01-20

申请号：EP14730231.9

申请日：2014-03-12

Applicant: Qualcomm Incorporated

Inventor： INGLE, Ajay, Anant ,  HOYLE, David, J. ,  HOFFMAN, Marc, M.

IPC: G06F9/30

CPC classification number: G06F15/8053 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109

Abstract: An example method for placing one or more element data values into an output vector includes identifying a vertical permute control vector including a plurality of elements, each element of the plurality of elements including a register address. The method also includes for each element of the plurality of elements, reading a register address from the vertical permute control vector. The method further includes retrieving a plurality of element data values based on the register address. The method also includes identifying a horizontal permute control vector including a set of addresses corresponding to an output vector. The method further includes placing at least some of the retrieved element data values of the plurality of element data values into the output vector based on the set of addresses in the horizontal permute control vector.

公开(公告)号：EP2962187B1

公开(公告)日：2018-03-28

申请号：EP14709827.1

申请日：2014-02-21

Applicant: Qualcomm Incorporated

Inventor： INGLE, Ajay, Anant ,  HOFFMAN, Marc, M. ,  FRIDMAN, Jose ,  CODRESCU, Lucian

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/345

CPC classification number: G06F9/30105 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30163 ,  G06F9/345 ,  G06F9/3885

Abstract: Techniques are provided for executing a vector alignment instruction. A scalar register file in a first processor is configured to share one or more register values with a second processor, the one or more register values accessed from the scalar register file according to an Rt address specified in a vector alignment instruction, wherein a start location is determined from one of the shared register values. An alignment circuit in the second processor is configured to align data identified between the start location within a beginning Vu register of a vector register file (VRF) and an end location of a last Vu register of the VRF according to the vector alignment instruction. A store circuit is configured to select the aligned data from the alignment circuit and store the aligned data in the vector register file according to an alignment store address specified by the vector alignment instruction.

公开(公告)号：EP2962187A2

公开(公告)日：2016-01-06

申请号：EP14709827.1

申请日：2014-02-21

Applicant: Qualcomm Incorporated

Inventor： INGLE, Ajay, Anant ,  HOFFMAN, Marc, M. ,  FRIDMAN, Jose ,  CODRESCU, Lucian

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/345

CPC classification number: G06F9/30105 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30163 ,  G06F9/345 ,  G06F9/3885

Abstract: Techniques are provided for executing a vector alignment instruction. A scalar register file in a first processor is configured to share one or more register values with a second processor, the one or more register values accessed from the scalar register file according to an Rt address specified in a vector alignment instruction, wherein a start location is determined from one of the shared register values. An alignment circuit in the second processor is configured to align data identified between the start location within a beginning Vu register of a vector register file (VRF) and an end location of a last Vu register of the VRF according to the vector alignment instruction. A store circuit is configured to select the aligned data from the alignment circuit and store the aligned data in the vector register file according to an alignment store address specified by the vector alignment instruction.

公开(公告)号：EP2802993A1

公开(公告)日：2014-11-19

申请号：EP13700444.6

申请日：2013-01-10

Applicant: Qualcomm Incorporated

Inventor： PLONDKE, Erich, James ,  INGLE, Ajay, Anant ,  CODRESCU, Lucian

IPC: G06F12/10 ,  G06F9/30 ,  G06F12/08

CPC classification number: G06F12/0811 ,  G06F12/0888 ,  G06F12/1027

Abstract: Systems and methods for performing non-allocating memory access instructions with physical address. A system includes a processor, one or more levels of caches, a memory, a translation look-aside buffer (TLB), and a memory access instruction specifying a memory access by the processor and an associated physical address. Execution logic is configured to bypass the TLB for the memory access instruction and perform the memory access with the physical address, while avoiding allocation of one or more intermediate levels of caches where a miss may be encountered.