公开(公告)号：WO2016134070A1

公开(公告)日：2016-08-25

申请号：PCT/US2016/018345

申请日：2016-02-17

Applicant: QUALCOMM INCORPORATED

Inventor： JOW, Uei-Ming ,  SONG, Young Kyu ,  LEE, Jong-Hoon ,  ZHANG, Xiaonan ,  VELEZ, Mario Francisco

IPC: H01L23/498

CPC classification number: H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/17 ,  H01L2224/0401 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2924/15311

Abstract: An integrated circuit device that includes a package substrate and a die coupled to the package substrate. The package substrate includes at least one dielectric layer, a first stack of first interconnects in the at least one dielectric layer, and a second interconnect formed on at least one side portion of the at least one dielectric layer. The first stack of first interconnects is configured to provide a first electrical path for a non-ground reference signal, where the first stack of first interconnects is located along at least one side of the package substrate. The second interconnect is configured to provide a second electrical path for a ground reference signal.

Abstract translation: 一种集成电路器件，包括封装衬底和耦合到封装衬底的管芯。 所述封装衬底包括至少一个电介质层，所述至少一个电介质层中的第一互连的第一叠层以及形成在所述至少一个电介质层的至少一个侧部上的第二互连。 第一互连的第一堆叠被配置为提供用于非接地参考信号的第一电路，其中第一互连的第一堆叠沿着封装衬底的至少一侧设置。 第二互连被配置为提供用于接地参考信号的第二电路径。

公开(公告)号：EP3259777A1

公开(公告)日：2017-12-27

申请号：EP16708549.7

申请日：2016-02-17

Applicant: Qualcomm Incorporated

Inventor： JOW, Uei-Ming ,  SONG, Young Kyu ,  LEE, Jong-Hoon ,  ZHANG, Xiaonan ,  VELEZ, Mario Francisco

IPC: H01L23/498

CPC classification number: H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/17 ,  H01L2224/0401 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2924/15311

Abstract: An integrated circuit device that includes a package substrate and a die coupled to the package substrate. The package substrate includes at least one dielectric layer, a first stack of first interconnects in the at least one dielectric layer, and a second interconnect formed on at least one side portion of the at least one dielectric layer. The first stack of first interconnects is configured to provide a first electrical path for a non-ground reference signal, where the first stack of first interconnects is located along at least one side of the package substrate. The second interconnect is configured to provide a second electrical path for a ground reference signal.

公开(公告)号：EP3311389A1

公开(公告)日：2018-04-25

申请号：EP16730638.0

申请日：2016-06-06

Applicant: Qualcomm Incorporated

Inventor： JOW, Uei-Ming ,  SONG, Young Kyu ,  LEE, Jong-Hoon ,  YOON, Jung Ho ,  CHOI, Sangjo ,  ZHANG, Xiaonan

IPC: H01F17/00 ,  H01F41/04

Abstract: An inductor structure includes a first set of traces corresponding to a first layer of an inductor, a second set of traces corresponding to a second layer of the inductor, and a third set of traces corresponding to a third layer of the inductor that is positioned between the first layer and the second layer. The first set of traces includes a first trace and a second trace that is parallel to the first trace. A dimension of the first trace is different from a corresponding dimension of the second trace. The second set of traces is coupled to the first set of traces. The second set of traces includes a third trace that is coupled to the first trace and to the second trace. The third set of traces is coupled to the first set of traces.

公开(公告)号：WO2016209602A1

公开(公告)日：2016-12-29

申请号：PCT/US2016/036079

申请日：2016-06-06

Applicant: QUALCOMM INCORPORATED

Inventor： JOW, Uei-Ming ,  SONG, Young Kyu ,  LEE, Jong-Hoon ,  YOON, Jung Ho ,  CHOI, Sangjo ,  ZHANG, Xiaonan

IPC: H01F17/00 ,  H01F41/04

CPC classification number: H01F27/2804 ,  H01F17/0006 ,  H01F17/0013 ,  H01F41/041 ,  H01F2027/2809

Abstract: An inductor structure includes a first set of traces corresponding to a first layer of an inductor, a second set of traces corresponding to a second layer of the inductor, and a third set of traces corresponding to a third layer of the inductor that is positioned between the first layer and the second layer. The first set of traces includes a first trace and a second trace that is parallel to the first trace. A dimension of the first trace is different from a corresponding dimension of the second trace. The second set of traces is coupled to the first set of traces. The second set of traces includes a third trace that is coupled to the first trace and to the second trace. The third set of traces is coupled to the first set of traces.

Abstract translation: 电感器结构包括对应于电感器的第一层的第一组迹线，对应于电感器的第二层的第二组迹线，以及对应于电感器的第三层的第三组迹线，其位于 第一层和第二层。 第一组轨迹包括与第一轨迹平行的第一轨迹和第二轨迹。 第一个跟踪的维度与第二个跟踪的相应维度不同。 第二组迹线耦合到第一组迹线。 第二组迹线包括耦合到第一迹线和第二迹线的第三迹线。 第三组迹线耦合到第一组迹线。

公开(公告)号：WO2017053560A1

公开(公告)日：2017-03-30

申请号：PCT/US2016/053101

申请日：2016-09-22

Applicant: QUALCOMM INCORPORATED

Inventor： SONG, Young Kyu ,  LEE, Jong-Hoon ,  JOW, Uei-Ming

IPC: H01L23/538 ,  H01L25/16 ,  H01L21/60 ,  H01L25/065 ,  H01L23/552

CPC classification number: H01L23/552 ,  H01L21/4846 ,  H01L21/4853 ,  H01L23/498 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/20 ,  H01L25/065 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/24246 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81815 ,  H01L2224/83005 ,  H01L2224/83192 ,  H01L2224/92225 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06572 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/37001

Abstract: Provided is a low-profile package and related techniques for use and fabrication. In an example, a low-profile package is provided. The low-profile package includes an exemplary integrated circuit (IC) (112) having an active face (114), an integrated passive device (IPD) (102) having a face, and a redistribution layer (RDL) (106,108) disposed between the IPD and the IC. The IC is embedded in a substrate (104). The active face of the IC faces the face of the IPD in a face-to-face (F2F) configuration. At least one contact of the IPD is arranged in an overlapping configuration relative to the IC. The RDL is configured to electrically couple the IPD with the IC. The RDL can be disposed between the IPD and the IC, can be embedded in the substrate, and can be configured as an electromagnetic shield.

Abstract translation: 提供了一种低调的包装和相关的使用和制造技术。 在一个例子中，提供了一个薄型包装。 薄型封装包括具有有源面（114），具有面的集成无源器件（IPD）（102））和再分配层（RDL）（106,108）的示例性集成电路（112） IPD和IC。 IC嵌入基板（104）中。 IC的主动面以面对面（F2F）配置面对IPD的脸部。 IPD的至少一个触点以相对于IC的重叠配置布置。 RDL被配置为将IPD与IC电耦合。 RDL可以设置在IPD和IC之间，可以嵌入在基板中，并且可以配置为电磁屏蔽。

公开(公告)号：WO2016040518A1

公开(公告)日：2016-03-17

申请号：PCT/US2015/049238

申请日：2015-09-09

Applicant: QUALCOMM INCORPORATED

Inventor： YOON, Jung Ho ,  ZHANG, Xiaonan ,  LEE, Jong-Hoon ,  SONG, Young Kyu ,  JOW, Uei-Ming

IPC: H01L23/498 ,  H01F17/00 ,  H03H7/09 ,  H05K1/16

CPC classification number: H01L28/40 ,  H01F17/0006 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5223 ,  H01L23/5227 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/16237 ,  H01L2924/15311 ,  H05K1/112 ,  H05K1/116 ,  H05K1/16 ,  H05K1/162 ,  H05K1/165 ,  H05K3/3436 ,  H05K3/4007 ,  H05K3/4688 ,  H05K2201/094 ,  H05K2201/096 ,  H05K2201/09672 ,  H05K2201/10734

Abstract: A package substrate (or printed circuit board) that includes at least one dielectric layer, a first inductor structure is at least partially located in the dielectric layer, a third interconnect, and a second inductor structure. The first inductor structure includes a first interconnect, a first via coupled to the first interconnect, and a second interconnect coupled to the first via. The third interconnect is coupled to the first inductor structure. The third interconnect is configured to provide an electrical path for a ground signal. The second inductor structure is at least partially located in the dielectric layer. The second inductor is coupled to the third interconnect. The second inductor structure includes a fourth interconnect, a second via coupled to the fourth interconnect, and a fifth interconnect coupled to the second via. The first and second inductor structures are configured to operate with a capacitor as a 3 rd harmonic suppression filter.

Abstract translation: 包括至少一个介电层的封装基板（或印刷电路板），第一电感结构至少部分地位于介电层，第三互连和第二电感结构中。 第一电感器结构包括第一互连，耦合到第一互连的第一通路和耦合到第一通路的第二互连。 第三互连件耦合到第一电感器结构。 第三互连被配置为提供用于接地信号的电路径。 第二电感器结构至少部分地位于电介质层中。 第二电感器耦合到第三互连。 第二电感器结构包括第四互连，耦合到第四互连的第二通路和耦合到第二通路的第五互连。 第一和第二电感器结构被配置为用作为三次谐波抑制滤波器的电容器操作。

公开(公告)号：WO2016036744A2

公开(公告)日：2016-03-10

申请号：PCT/US2015/047953

申请日：2015-09-01

Applicant: QUALCOMM INCORPORATED

Inventor： JOW, Uei-Ming ,  SONG, Young Kyu ,  YOON, Jung Ho ,  LEE, Jong-Hoon ,  ZHANG, Xiaonan

IPC: H01L23/528

CPC classification number: H01L23/5286 ,  H01F27/2804 ,  H01F2017/0086 ,  H01L21/4828 ,  H01L23/3121 ,  H01L23/495 ,  H01L23/49548 ,  H01L23/49838 ,  H01L23/5227 ,  H01L23/645 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L28/10 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A semiconductor package according to some examples of the disclosure may include a first body layer, a transformer that may comprise one or more inductors, coupled inductors, or inductive elements positioned above the first body layer. A first ground plane is on a top of the first body layer between the first body layer and the inductive element. The first ground plane may have conductive lines generally perpendicular to a magnetic field generated by the inductive element, and a second ground plane on a bottom of the first body layer opposite the first ground plane. The first and second ground planes may also provide heat dissipation elements for the semiconductor as well as reduce or eliminate eddy current and parasitic effects produced by the inductive element.

Abstract translation: 根据本公开的一些示例的半导体封装可以包括第一体层，可包括位于第一体层上方的一个或多个电感器，耦合电感器或电感元件的变压器。 第一接地平面位于第一体层和感应元件之间的第一体层的顶部。 第一接地平面可以具有大致垂直于由感应元件产生的磁场的导线，以及与第一接地平面相对的第一体层底部的第二接地平面。 第一和第二接地平面还可以为半导体提供散热元件，以及减少或消除由电感元件产生的涡流和寄生效应。

公开(公告)号：WO2017048500A1

公开(公告)日：2017-03-23

申请号：PCT/US2016/049440

申请日：2016-08-30

Applicant: QUALCOMM INCORPORATED

Inventor： LEE, John, Jong-Hoon ,  SONG, Young, Kyu ,  JOW, Uei-Ming ,  CHOI, Sangjo ,  ZHANG, Xiaonan

IPC: H01P7/06

CPC classification number: H01P1/207 ,  H01L21/4853 ,  H01L23/5222 ,  H01L23/5227 ,  H01L23/552 ,  H01L23/60 ,  H01L23/66 ,  H01L24/16 ,  H01L28/10 ,  H01L28/40 ,  H01L2223/6627 ,  H01L2223/6666 ,  H01L2223/6672 ,  H01L2224/10 ,  H01L2224/16227 ,  H01P1/201 ,  H01P7/06 ,  H01P7/065 ,  H03B5/1817 ,  H05K1/0243

Abstract: A flip-chip employing an integrated cavity filter is disclosed comprising an integrated circuit (IC) chip comprising a semiconductor die and a plurality of conductive bumps. The plurality of conductive bumps is interconnected to at least one metal layer of the semiconductor die to provide a conductive "fence" that defines an interior resonator cavity for providing an integrated cavity filter in the flip-chip. The interior resonator cavity is configured to receive an input RF signal from an input transmission line through an input signal transmission aperture provided in an internal layer in the semiconductor die. The interior resonator cavity resonates the input RF signal to generate the output RF signal comprising a filtered RF signal of the input RF signal, and couples the output RF signal on an output signal transmission line in the flip-chip through an output transmission aperture provided in the aperture layer.

Abstract translation: 公开了一种采用集成腔滤波器的倒装芯片，其包括集成电路（IC）芯片，其包括半导体管芯和多个导电凸块。 多个导电凸块互连到半导体管芯的至少一个金属层，以提供限定用于在倒装芯片中提供集成腔滤波器的内部谐振腔的导电“栅栏”。 内部谐振器腔被配置为通过设置在半导体管芯中的内层中的输入信号传输孔从输入传输线接收输入RF信号。 内部谐振腔谐振输入RF信号以产生包括输入RF信号的滤波RF信号的输出RF信号，并且通过输出传输孔将输出RF信号耦合在倒装芯片中的输出信号传输线上 孔径层。

公开(公告)号：WO2016133685A3

公开(公告)日：2016-08-25

申请号：PCT/US2016/016001

申请日：2016-02-01

Applicant: QUALCOMM INCORPORATED

Inventor： JOW, Uei-Ming ,  SONG, Young Kyu ,  LEE, Jong-Hoon ,  ZHANG, Xiaonan

IPC: H01L49/02 ,  H01G4/33 ,  H01L23/522 ,  H01L23/64

Abstract: An upper planar capacitor (204) is spaced above a lower planar capacitor (102) by a dielectric layer (201). A bridged-post inter-layer connector couples the capacitances in parallel, through first posts (210A,C) and second posts (210B,D). The first posts and second posts extend through the dielectric layer, adjacent the upper and lower planar capacitors. A first level coupler (106) extends under the dielectric layer and couples the first posts together and to a conductor of the lower planar capacitor, and couples another conductor of the lower planar capacitor to one of the second posts. A second level coupler (212) extends above the dielectric layer, and couples the second posts together and to a conductor of the upper planar capacitor, and couples another conductor of the upper planar capacitor to one of the first posts.

公开(公告)号：WO2016100267A1

公开(公告)日：2016-06-23

申请号：PCT/US2015/065687

申请日：2015-12-15

Applicant: QUALCOMM INCORPORATED

Inventor： YOON, Jung Ho ,  SONG, Young Kyu ,  JOW, Uei-Ming ,  LEE, Jong-Hoon ,  ZHANG, Xiaonan

IPC: H01L23/492 ,  H01L23/538 ,  H01L23/66 ,  H01L23/498

CPC classification number: H01L23/49541 ,  H01L21/4825 ,  H01L23/492 ,  H01L23/49517 ,  H01L23/49524 ,  H01L23/49568 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/24246 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244

Abstract: A semiconductor package according to some examples may include a first portion of a support plate configured as an RF signal connection, a semiconductor die thermally coupled to a second portion of the support plate to dissipate heat, a first redistribution layer positioned in close proximity to a second redistribution layer to capacitively couple the first redistribution layer to the second redistribution layer, a first via extending between the first portion and the first redistribution layer, and a second via in close proximity to the first via to capacitively couple the second via to the first via.

Abstract translation: 根据一些示例的半导体封装可以包括被配置为RF信号连接的支撑板的第一部分，热耦合到支撑板的第二部分以散热的半导体管芯，第一再分布层位于紧邻 第二再分布层，以将第一再分布层电容耦合到第二再分配层，在第一部分和第一再分布层之间延伸的第一通孔，以及紧邻第一通孔的第二通孔，以将第二通孔电容耦合到第一通路 通过。