公开(公告)号：WO2002067420A3

公开(公告)日：2002-08-29

申请号：PCT/US2002/004727

申请日：2002-02-15

Applicant: QUALCOMM INCORPORATED

Inventor： LI, Tao ,  HOLENSTEIN, Christian ,  KANG, Injup ,  WALKER, Brett, C. ,  PETERZELL, Paul, E. ,  CHALLA, Raghu ,  SEVERSON, Matthew, L.

IPC: H03G3/30

Abstract: A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.

公开(公告)号：WO2002067420A2

公开(公告)日：2002-08-29

申请号：PCT/US2002/004727

申请日：2002-02-15

Applicant: QUALCOMM INCORPORATED

Inventor： LI, Tao ,  HOLENSTEIN, Christian ,  KANG, Injup ,  WALKER, Brett, C. ,  PETERZELL, Paul, E. ,  CHALLA, Raghu ,  SEVERSON, Matthew, L.

IPC: H03G

CPC classification number: H03G3/3078 ,  H03G3/3068 ,  H03G3/3089

Abstract: A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.

Abstract translation: 具有用于去除信号分量的DC偏移的DC环路的直接下变频接收机架构，提供一系列增益的数字可变增益放大器（DVGA），用于为DVGA和RF提供增益控制的自动增益控制（AGC）回路 /模拟电路和串行总线接口（SBI）单元，通过串行总线为RF /模拟电路提供控制。 可以如本文所述有利地设计和定位DVGA。 可以基于DC循环的操作模式来选择VGA循环的操作模式，因为这两个循环彼此相互作用。 在采集模式中DC环路工作的持续时间可以被选择为与采集模式中的DC环路带宽成反比。 一些或全部RF /模拟电路的控制可以通过串行总线提供。

公开(公告)号：EP1402631B1

公开(公告)日：2011-05-18

申请号：EP02709570.2

申请日：2002-02-15

Applicant: QUALCOMM INCORPORATED

Inventor： LI, Tao ,  HOLENSTEIN, Christian ,  KANG, Injup ,  WALKER, Brett, C. ,  PETERZELL, Paul, E. ,  CHALLA, Raghu ,  SEVERSON, Matthew, L. ,  RAGHUPATHY, Arun ,  SIH, Gilbert C.

IPC: H03G3/30 ,  H03D3/00 ,  H04B1/40

CPC classification number: H03G3/3078 ,  H03G3/3068 ,  H03G3/3089

Abstract: A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.

公开(公告)号：EP1402631A2

公开(公告)日：2004-03-31

申请号：EP02709570.2

申请日：2002-02-15

Applicant: QUALCOMM INCORPORATED

Inventor： LI, Tao ,  HOLENSTEIN, Christian ,  KANG, Injup ,  WALKER, Brett, C. ,  PETERZELL, Paul, E. ,  CHALLA, Raghu ,  SEVERSON, Matthew, L.

IPC: H03G3/30 ,  H03D3/00 ,  H04B1/40

CPC classification number: H03G3/3078 ,  H03G3/3068 ,  H03G3/3089

Abstract: A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.