公开(公告)号：WO2015175094A1

公开(公告)日：2015-11-19

申请号：PCT/US2015/022055

申请日：2015-03-23

Applicant: QUALCOMM INCORPORATED

Inventor： TASIC, Aleksandar Miodrag ,  NARATHONG, Chiewcharn ,  HOLENSTEIN, Christian ,  PAN, Dongling ,  TANG, Yiwu ,  RANGARAJAN, Rajagopalan ,  LEUNG, Lai Kan

IPC: H04B1/00 ,  H03F1/22

CPC classification number: H04L27/2653 ,  H03F1/223 ,  H03F3/193 ,  H03F3/245 ,  H04B1/0064 ,  H04L45/16 ,  H04L45/245

Abstract: Multiplex modules for use in carrier aggregation receivers are disclosed. In an exemplary embodiment, an apparatus includes an LNA multiplexer configured to receive a plurality of RF signals at a plurality of input terminals and to combine the RF signals into a combined RF signal that is output from an output terminal. The apparatus also includes an LNA demultiplexer configured to receive the combined RF signal at an input port that is connected to the output terminal and to distribute the combined RF signal to a plurality of output ports.

Abstract translation: 公开了用于载波聚合接收机的多路复用模块。 在示例性实施例中，一种装置包括LNA多路复用器，其被配置为在多个输入端子处接收多个RF信号，并将RF信号组合成从输出端输出的组合RF信号。 该装置还包括LNA解复用器，其被配置为在连接到输出端子的输入端口处接收组合的RF信号，并将组合的RF信号分配到多个输出端口。

公开(公告)号：EP1402631B1

公开(公告)日：2011-05-18

申请号：EP02709570.2

申请日：2002-02-15

Applicant: QUALCOMM INCORPORATED

Inventor： LI, Tao ,  HOLENSTEIN, Christian ,  KANG, Injup ,  WALKER, Brett, C. ,  PETERZELL, Paul, E. ,  CHALLA, Raghu ,  SEVERSON, Matthew, L. ,  RAGHUPATHY, Arun ,  SIH, Gilbert C.

IPC: H03G3/30 ,  H03D3/00 ,  H04B1/40

CPC classification number: H03G3/3078 ,  H03G3/3068 ,  H03G3/3089

Abstract: A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.

公开(公告)号：WO2014116674A1

公开(公告)日：2014-07-31

申请号：PCT/US2014/012509

申请日：2014-01-22

Applicant: QUALCOMM INCORPORATED

Inventor： HOLENSTEIN, Christian ,  TASIC, Aleksandar Miodrag ,  CHANG, Li-Chung ,  HE, Allen

IPC: H03F1/02 ,  H03F1/22 ,  H03F3/193 ,  H03F3/68 ,  H03F3/72

CPC classification number: H04B1/16 ,  H03F1/0277 ,  H03F1/223 ,  H03F3/193 ,  H03F3/68 ,  H03F3/72 ,  H03F2200/111 ,  H03F2200/294 ,  H03F2200/489 ,  H03F2200/492 ,  H03F2200/541 ,  H03G3/30 ,  H03G3/3052 ,  H03G5/24 ,  H04W88/06

Abstract: Amplifiers with multiple outputs and separate gain control per output are disclosed. In an exemplary design, an apparatus (e.g., a wireless device or an integrated circuit) may include first (640) and second (660) amplifier circuits. The first amplifier circuit (640) may receive and amplify an input radio frequency, RF, signal (RFin) based on a first variable gain and provide a first amplified RF signal (RFampl). The second amplifier circuit (660) may receive and amplify the input RF signal (RFin) based on a second variable gain and provide a second amplified RF signal (RFamp2). The input RF signal may include a plurality of transmitted signals being received by the wireless device. The first variable gain may be adjustable independently of the second variable gain. Each variable gain may be set based on the received power level of at least one transmitted signal being received by the wireless device.

Abstract translation: 公开了具有多个输出和每个输出的单独的增益控制的放大器。 在示例性设计中，装置（例如，无线装置或集成电路）可以包括第一（640）和第二（660）放大器电路。 第一放大器电路（640）可以基于第一可变增益接收和放大输入射频，RF信号（RFin），并提供第一放大RF信号（RFampl）。 第二放大器电路（660）可以基于第二可变增益接收和放大输入RF信号（RFin），并提供第二放大RF信号（RFamp2）。 输入RF信号可以包括由无线设备接收的多个发送信号。 第一可变增益可以独立于第二可变增益来调节。 可以基于由无线设备接收的至少一个发送信号的接收功率电平来设置每个可变增益。

公开(公告)号：WO2010151650A1

公开(公告)日：2010-12-29

申请号：PCT/US2010/039795

申请日：2010-06-24

Applicant: QUALCOMM INCORPORATED ,  SAMPATH, Hemanth ,  HOLENSTEIN, Christian ,  LIN, Jeremy, Huei ,  KADOUS, Tamer, A. ,  MARRA, Thomas, D.

Inventor： SAMPATH, Hemanth ,  HOLENSTEIN, Christian ,  LIN, Jeremy, Huei ,  KADOUS, Tamer, A. ,  MARRA, Thomas, D.

IPC: H03M1/66 ,  H04B1/00

CPC classification number: H03M1/66 ,  H04B1/005

Abstract: A method for interference reduction is described. A sampling frequency is selected for a digital-to-analog converter (DAC) so that images within a DAC output signal do not interfere with one or more receivers. A sample rate is adjusted of an input signal that is provided to the DAC to match the sampling frequency for the DAC.

Abstract translation: 描述了一种减少干扰的方法。 为数模转换器（DAC）选择采样频率，以便DAC输出信号中的图像不会干扰一个或多个接收器。 调整提供给DAC的输入信号以与DAC的采样频率匹配的采样率。

公开(公告)号：WO2004021589A1

公开(公告)日：2004-03-11

申请号：PCT/US2003/027016

申请日：2003-08-28

Applicant: QUALCOMM INCORPORATED

Inventor： SCHLEGEL, Nikolai ,  HOLENSTEIN, Christian ,  FILIPOVIC, Daniel ,  KASTURI, Nitin

IPC: H04B1/30

CPC classification number: H04L25/063 ,  H03D3/008 ,  H04B1/30

Abstract: An apparatus for coarse compensation of a direct current (DC) offset in a direct to baseband receiver architecture utilizes a serial analog to digital converter (ADC), such as a Delta-Sigma converter, to convert the received signal to digital form. The output of the ADC is sampled for a predetermined number of samples and a counter coupled to the ADC is incremented each time the sample generated by the ADC is a logic one. The counter is not incremented if the sample from the ADC is a logic zero. After the predetermined number of samples is obtained, the counter value is indicative of the DC offset in the received signal. The counter value may be converted by a code converter to a correction value for easy operation of a digital to analog converter (DAC). If the number of samples from the ADC is a power of two, the code converted may be readily implemented by simply inverting the most significant bit (MSB) from the counter to thereby generate a twos complement version of the counter value. The correction value is coupled to the DAC to generate a compensation signal, which is provided to the received signal path in the form of a feedback signal to compensate for the DC offset.

Abstract translation: 直接到基带接收器架构中用于粗略补偿直流（DC）偏移的装置利用诸如Delta-Sigma转换器的串行模数转换器（ADC）将接收到的信号转换为数字形式。 ADC的输出对预定数量的采样进行采样，并且每当ADC产生的采样为逻辑1时，耦合到ADC的计数器递增。 如果来自ADC的采样是逻辑0，则计数器不会递增。 在获得预定数量的样本之后，计数器值指示接收信号中的DC偏移。 计数器值可由代码转换器转换为校正值，以便于数字模拟转换器（DAC）的操作。 如果来自ADC的采样数是2的幂，则转换的代码可以通过简单地反转来自计数器的最高有效位（MSB）来实现，从而生成计数器值的二进制补码版本。 校正值耦合到DAC以产生补偿信号，该补偿信号以反馈信号的形式提供给接收信号路径以补偿DC偏移。

公开(公告)号：WO2009117707A1

公开(公告)日：2009-09-24

申请号：PCT/US2009/037884

申请日：2009-03-20

Applicant: QUALCOMM Incorporated ,  HOLENSTEIN, Christian ,  DENG, Junxiong ,  KIM, Namsoo

Inventor： HOLENSTEIN, Christian ,  DENG, Junxiong ,  KIM, Namsoo

IPC: H04B1/16 ,  H03D7/00

CPC classification number: H04W52/0206 ,  H03G3/20 ,  H04B1/16

Abstract: An exemplary embodiment disclosed comprises a mixer having a plurality of input leads; a first degenerative impedance element coupled to a first input lead of the mixer; a second degenerative impedance element coupled to a second input lead of the mixer; and a local oscillator (LO) system comprising a plurality of duty cycle modes to generate a LO signal for the mixer, the local oscillator system operates in a first duty cycle based on a first gain state of the mixer, and in a second duty cycle based on a second gain state of the mixer.

Abstract translation: 公开的示例性实施例包括具有多个输入引线的混合器; 耦合到混合器的第一输入引线的第一退化阻抗元件; 耦合到混合器的第二输入引线的第二退化阻抗元件; 以及本地振荡器（LO）系统，其包括多个占空比模式以产生混频器的LO信号，本地振荡器系统基于混频器的第一增益状态在第一占空比中工作，并且在第二占空比 基于混频器的第二增益状态。

公开(公告)号：WO2009100387A1

公开(公告)日：2009-08-13

申请号：PCT/US2009/033474

申请日：2009-02-06

Applicant: QUALCOMM Incorporated ,  HOLENSTEIN, Christian ,  DENG, Junxiong ,  KIM, Namsoo

Inventor： HOLENSTEIN, Christian ,  DENG, Junxiong ,  KIM, Namsoo

IPC: H03F3/45 ,  H03F3/193 ,  H03F1/32 ,  H03G1/00

CPC classification number: H03F3/193 ,  H03F1/3205 ,  H03F1/3211 ,  H03F3/45188 ,  H03F2200/294 ,  H03F2200/357 ,  H03F2200/451 ,  H03F2203/45246 ,  H03F2203/45318 ,  H03F2203/45386 ,  H03F2203/45396 ,  H03G1/0029

Abstract: A differential low noise amplifier (LNA) is operable in a selectable one of two modes. The LNA includes a first transistor (204), a second transistor (205), a third transistor (206) and a fourth transistor. In the first mode (PDC mode), the four transistors are configured to operate as a post-distortion cancellation (PDC) LNA. The third (206) and fourth (207) transistors operate as cancel transistors that improve linearity, but reduce LNA gain somewhat. In the second mode (high gain mode), the third (206) and fourth (207) transistors are configured so that amplified versions of the LNA input signal that they output are added to amplified versions of the LNA input signal that are output by the first and second main transistors (204, 205), resulting in increased gain. Multiplexing circuits are provided within the LNA so that the LNA is configurable into a selectable one of the two modes by controlling a digital mode control signal supplied to the LNA.

Abstract translation: 差分低噪声放大器（LNA）可在两种模式中的一种选择中操作。 LNA包括第一晶体管（204），第二晶体管（205），第三晶体管（206）和第四晶体管。 在第一模式（PDC模式）中，四个晶体管被配置为作为后失真消除（PDC）LNA而工作。 第三（206）和第四（207）晶体管作为提高线性度的抵消晶体管工作，但有一些降低LNA增益。 在第二模式（高增益模式）中，第三（206）和第（207）晶体管被配置为使得它们输出的LNA输入信号的放大版本被加到由LNA输入信号输出的LNA输入信号的放大版本 第一和第二主晶体管（204,205），导致增益增加。 在LNA中提供多路复用电路，使得LNA可以通过控制提供给LNA的数字模式控制信号来配置成两种模式中的可选择的一种。

公开(公告)号：WO2003088606A3

公开(公告)日：2003-10-23

申请号：PCT/US2003/011070

申请日：2003-04-09

Applicant: QUALCOMM INCORPORATED

Inventor： HOLENSTEIN, Christian ,  KANG, Inyup ,  SEVERSON, Matthew

IPC: H04L25/06

Abstract: A system and method for canceling DC offset for Mobile Station Modems having direct conversion architectures. The present invention is a fast acquiring DC offset cancellation block that provides rapid and accurate DC offset estimates and cancellation techniques to support direct conversion architectures. The fast acquiring DC offset cancellation block combines four mechanisms to rapidly acquire and remove a DC offset estimate after power up, temperature changes, receiver frequency changes, and gain setting changes by increasing high pass loop bandwidth and adjusting DC offset levels at baseband. After removing the DC offset in large portions, the high pass loop bandwidth is decreased to fine tune the previous estimate and to remove any small variation in DC offset due to receiver self-mixing products.

公开(公告)号：WO2002067420A3

公开(公告)日：2002-08-29

申请号：PCT/US2002/004727

申请日：2002-02-15

Applicant: QUALCOMM INCORPORATED

Inventor： LI, Tao ,  HOLENSTEIN, Christian ,  KANG, Injup ,  WALKER, Brett, C. ,  PETERZELL, Paul, E. ,  CHALLA, Raghu ,  SEVERSON, Matthew, L.

IPC: H03G3/30

Abstract: A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.

公开(公告)号：WO2014043270A1

公开(公告)日：2014-03-20

申请号：PCT/US2013/059308

申请日：2013-09-11

Applicant: QUALCOMM INCORPORATED

Inventor： CHANG, Li-Chung ,  GUDEM, Prasad Srinivasa Siva ,  BOSSU, Frederic ,  HOLENSTEIN, Christian

IPC: H04B1/00 ,  H04B1/28

CPC classification number: H04J3/00 ,  H03F3/72 ,  H04B1/0064 ,  H04B1/0071

Abstract: A receiver architecture for carrier aggregation is disclosed. In an exemplary design, an apparatus (e.g., a wireless device, a circuit module, etc.) includes a plurality of low noise amplifiers (LNAs), a plurality of switches, and at least one downconverter. The LNAs receive and amplify at least one input radio frequency (RF) signal and provide at least one amplified RF signal. The switches are coupled to the outputs of the plurality of LNAs. The at least one downconverter is coupled to the plurality of switches, downconverts the at least one amplified RF signal, and provides at least one downconverted signal. The switches reduce the number of downconverters needed to support reception of transmissions on multiple sets of carriers via multiple receive antennas. The LNAs and the switches may be implemented on at least one front-end module or a back-end module. The downconverter(s) are implemented on the back-end module.

Abstract translation: 公开了用于载波聚合的接收机架构。 在示例性设计中，装置（例如，无线装置，电路模块等）包括多个低噪声放大器（LNA），多个开关和至少一个下变频器。 LNA接收和放大至少一个输入射频（RF）信号并提供至少一个放大的RF信号。 开关耦合到多个LNA的输出端。 所述至少一个下变频器耦合到所述多个开关，对所述至少一个放大的RF信号进行下变频，并提供至少一个下变频信号。 交换机减少了通过多个接收天线支持在多组载波上接收传输所需的下变频器的数量。 LNA和交换机可以在至少一个前端模块或后端模块上实现。 下变频器在后端模块上实现。