公开(公告)号：EP3436959A1

公开(公告)日：2019-02-06

申请号：EP17711940.1

申请日：2017-03-03

Applicant: QUALCOMM Incorporated

Inventor： LI, Yanru ,  CHUN, Dexter Tamio ,  ARTIERI, Alain

IPC: G06F13/16 ,  G06F1/32

公开(公告)号：EP3256952B1

公开(公告)日：2018-12-05

申请号：EP16708511.7

申请日：2016-02-05

Applicant: Qualcomm Incorporated

Inventor： CHUN, Dexter Tamio ,  LI, Yanru

IPC: G06F13/16 ,  G06F9/48

CPC classification number: G06F13/26 ,  G06F9/4818 ,  G06F13/18

Abstract: Systems, methods, and computer programs are disclosed for scheduling volatile memory maintenance events. One embodiment is a method comprising: a memory controller determining a time-of-service (ToS) window for executing a maintenance event for a volatile memory device coupled to the memory controller via a memory data interface; the memory controller providing an interrupt signal to a processing unit; determining a priority for the maintenance event; and scheduling the maintenance event according to the priority.

公开(公告)号：EP3030949A1

公开(公告)日：2016-06-15

申请号：EP14756166.6

申请日：2014-08-07

Applicant: Qualcomm Incorporated

Inventor： CHUN, Dexter ,  LI, Yanru ,  TU, Alex ,  LO, Haw-jing

IPC: G06F1/32 ,  G06F12/06

CPC classification number: G06F1/3275 ,  G06F12/0607 ,  G06F2212/1028 ,  G11C14/0009 ,  Y02D10/13 ,  Y02D10/14

Abstract: Systems and methods are disclosed for providing memory channel interleaving with selective power or performance optimization. One such method involves configuring a memory address map for two or more memory devices accessed via two or more respective memory channels with an interleaved region and a linear region. The interleaved region comprises an interleaved address space for relatively higher performance use cases. The linear region comprises a linear address space for relatively lower power use cases. Memory requests are received from one or more clients. The memory requests comprise a preference for power savings or performance. Received memory requests are assigned to the linear region or the interleaved region according to the preference for power savings or performance.

Abstract translation: 系统和方法是游离缺失盘用于提供存储器通道具有选择性功率或性能优化交织。 一个搜索方法包括配置存储器地址映射用于通过与交错的两个或更多respectivement存储器通道区域和线性区域访问的两个或更多个存储器设备。 的交织地址空间交错的区域包括相对更高的性能使用情况。 线性区域包括用于相对较低的功率使用情况的线性地址空间。 内存请求从一个或多个客户的好评。 存储请求包括用于节能和性能的偏好。 接收到的存储器请求被分配给线性区域或交错区域gemäß到偏爱功率节省或性能。

公开(公告)号：WO2022020225A1

公开(公告)日：2022-01-27

申请号：PCT/US2021/042148

申请日：2021-07-19

Applicant: QUALCOMM INCORPORATED

Inventor： LI, Yanru ,  CHUN, Dexter, Tamio

IPC: G06F21/79

Abstract: Various embodiments may include methods and systems for providing secure in-memory device access of a memory device by a system-on-a-chip (SOC). Various methods may include receiving a configuration message from the SOC for configuring a memory access control of the memory device, and configuring the memory access control based on the configuration message. Various embodiments may include receiving an access request message from the SOC requesting access to a memory base address and a memory access range of a memory cell array of the memory device, wherein the access request message includes a read/write operation. Various embodiments may include comparing the access request message with the configured memory access control to determine whether the access request message is allowable. Various embodiments may further include performing the read/write operation in response to determining that the access request message is allowable.

公开(公告)号：WO2019089155A1

公开(公告)日：2019-05-09

申请号：PCT/US2018/052240

申请日：2018-09-21

Applicant: QUALCOMM INCORPORATED

Inventor： LI, Yanru ,  TOUZNI, Azzedine ,  CHUN, Dexter Tamio

IPC: G06F21/81 ,  G06F21/79 ,  G06F1/3234 ,  G06F1/3287 ,  G06F21/57

Abstract: Systems and methods are disclosed for managing memory access for low-power use cases of a system on chip. One such method comprises booting a system on chip (SoC) comprising a plurality of SoC processing devices. A trusted channel is created to a secure non-volatile random access memory (NVRAM). The method determines a power-saving software program to be executed on the SoC by one of the plurality of SoC processing devices. A software image associated with the power-saving software program is loaded to the secure NVRAM. In response to loading the software image to the secure NVRAM, each of the plurality of SoC processing devices except the one executing the software image from the secure NVRAM are powered down.

公开(公告)号：WO2018187165A3

公开(公告)日：2018-10-11

申请号：PCT/US2018/025243

申请日：2018-03-29

Applicant: QUALCOMM INCORPORATED

Inventor： PACKER ALI, Dhamim ,  CHALAMCHARLA, Sreenivasulu Reddy ,  PAREKH, Ruchi ,  DAVIS KOOLA, Daison ,  PATEL, Dhaval ,  TASESKI, Eric ,  LI, Yanru ,  GANTMAN, Alexander

IPC: G06F9/4401 ,  G06F9/445 ,  G06F21/57 ,  G06F1/32

Abstract: Various additional and alternative aspects are described herein. In some aspects, the present disclosure provides a method of calibrating a component. The method includes receiving previous calibration parameters for an external component at a secondary SoC from a primary SoC, wherein the secondary SoC is coupled to the extemal component and configured to calibrate the external component. The method further includes determining validity of the previous calibration parameters by the secondary SoC. The method further includes operating the external component by the secondary SoC based on the determined validity of the previous calibration parameters.

公开(公告)号：WO2017222752A1

公开(公告)日：2017-12-28

申请号：PCT/US2017/034858

申请日：2017-05-26

Applicant: QUALCOMM INCORPORATED

Inventor： DE, Subrato Kumar ,  CHUN, Dexter ,  LI, Yanru

IPC: G06F9/445 ,  G06F12/02

Abstract: Systems, methods, and computer programs are disclosed for scheduling decompression of an application from flash storage. One embodiment of a system comprises a flash memory device and a preemptive decompression scheduler component. The preemptive decompression scheduler component comprises logic configured to generate and store metadata defining one or more dependent objects associated with the compressed application in response to an application installer component installing a compressed application to the flash memory device. In response to a launch of the compressed application by an application launcher component, the preemptive decompression scheduler component determines from the stored metadata the one or more dependent objects associated with the compressed application to be launched. The preemptive decompression scheduler component preemptively schedules decompression of the one or more dependent objects based on the stored metadata.

Abstract translation: 公开了用于调度来自闪存的应用的解压缩的系统，方法和计算机程序。 系统的一个实施例包括闪存设备和抢先解压缩调度器组件。 抢先解压缩调度器组件包括被配置为响应于应用安装器组件将压缩应用安装到闪存设备而生成并存储定义与压缩应用相关联的一个或多个依赖对象的元数据的逻辑。 响应于由应用程序启动器组件启动压缩应用程序，抢先解压缩调度器组件从存储的元数据中确定与将要启动的压缩应用程序相关联的一个或多个依赖对象。 抢先解压缩调度器组件基于存储的元数据预先调度一个或多个依赖对象的解压缩。

公开(公告)号：WO2016130440A9

公开(公告)日：2016-08-18

申请号：PCT/US2016/016876

申请日：2016-02-05

Applicant: QUALCOMM INCORPORATED

Inventor： CHUN, Dexter Tamio ,  LI, Yanru ,  STEWART, Richard Alan ,  DE, Subrato Kumar

IPC: G06F13/16

Abstract: Systems, methods, and computer programs are disclosed for scheduling volatile memory maintenance events. One embodiment is a method comprising: a memory controller determining a time-of-service (ToS) window for executing a maintenance event for a volatile memory device coupled to the memory controller via a memory data interface; the memory controller providing a signal to each of a plurality of processors on a system on chip (SoC) for scheduling the maintenance event; each of the plurality of processors independently generating in response to the signal a corresponding schedule notification for the maintenance event; and the memory controller determining when to execute the maintenance event in response to receiving one or more of the schedule notifications generated by the plurality of processors and based on a processor priority scheme.

公开(公告)号：WO2016130439A1

公开(公告)日：2016-08-18

申请号：PCT/US2016/016874

申请日：2016-02-05

Applicant: QUALCOMM INCORPORATED

Inventor： CHUN, Dexter Tamio ,  LI, Yanru

IPC: G06F13/16 ,  G06F9/48

CPC classification number: G06F13/26 ,  G06F9/4818 ,  G06F13/18

Abstract: Systems, methods, and computer programs are disclosed for scheduling volatile memory maintenance events. One embodiment is a method comprising: a memory controller determining a time-of-service (ToS) window for executing a maintenance event for a volatile memory device coupled to the memory controller via a memory data interface; the memory controller providing an interrupt signal to a processing unit; determining a priority for the maintenance event; and scheduling the maintenance event according to the priority.

Abstract translation: 公开了用于调度易失性存储器维护事件的系统，方法和计算机程序。 一个实施例是一种方法，包括：存储器控制器，其确定用于经由存储器数据接口耦合到存储器控制器的易失性存储器设备执行维护事件的服务时间（ToS）窗口; 所述存储器控制器向处理单元提供中断信号; 确定维护事件的优先级; 并根据优先级调度维护事件。

公开(公告)号：WO2016040189A1

公开(公告)日：2016-03-17

申请号：PCT/US2015/048704

申请日：2015-09-04

Applicant: QUALCOMM INCORPORATED

Inventor： QUACH, Nhon Toai ,  LI, Yanru ,  KIMBERLY, William Edward

IPC: G06F9/52 ,  G06F3/06

CPC classification number: G06F12/0246 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0679 ,  G06F9/4401 ,  G06F12/0284 ,  Y02D10/154

Abstract: A computing device and methods for exposing a solid-state non-volatile memory element to multiple masters in a computing device are disclosed. A portion of a solid-state non-volatile memory element includes code and data for use by a non-boot processing resource. A host controller in communication with the solid-state non-volatile memory element is modified to receive and respond to a resource identifier unique to the processing resource that is requesting read access to the solid-state non-volatile memory element. Logic executed by a boot master and logic executed by a non-boot processing resource are synchronized in response to a set of indicators.

Abstract translation: 公开了一种用于将固态非易失性存储元件暴露于计算设备中的多个主器件的计算设备和方法。 固态非易失性存储元件的一部分包括由非引导处理资源使用的代码和数据。 与固态非易失性存储器元件通信的主机控制器被修改为接收和响应正在请求对固态非易失性存储器元件的读访问的处理资源唯一的资源标识符。 由引导主机执行的逻辑和由非引导处理资源执行的逻辑被响应于一组指示符而被同步。