公开(公告)号：WO2018160371A1

公开(公告)日：2018-09-07

申请号：PCT/US2018/018543

申请日：2018-02-17

Applicant: QUALCOMM INCORPORATED

Inventor： CHU, Jeffrey Hao ,  DE, Subrato Kumar ,  CHUN, Dexter Tamio ,  RYCHLIK, Bohuslav ,  STEWART, Richard Alan

IPC: G06F13/16 ,  G11C15/04

CPC classification number: G06F3/0656 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0673 ,  G06F13/1668 ,  G06F13/1673 ,  G11C15/043 ,  Y02D10/14

Abstract: Various aspects are described herein. In some aspects, the present disclosure provides a method of communicating data between an electronic unit of a system-onchip (SoC) and a dynamic random access memory (DRAM). The method includes initiating a memory transaction corresponding to first data. The method includes determining a non-unique first signature and a unique second signature associated with the first data based on content of the first data. The method includes determining if the non-unique first signature is stored in at least one of a local buffer on the SoC separate from the DRAM or the DRAM. The method includes determining if the unique second signature is stored in at least one of the local buffer or the DRAM based on determining the non-unique first signature is stored. The method includes eliminating the memory transaction with respect to the DRAM based on determining the unique second signature is stored.

公开(公告)号：WO2016130440A9

公开(公告)日：2016-08-18

申请号：PCT/US2016/016876

申请日：2016-02-05

Applicant: QUALCOMM INCORPORATED

Inventor： CHUN, Dexter Tamio ,  LI, Yanru ,  STEWART, Richard Alan ,  DE, Subrato Kumar

IPC: G06F13/16

Abstract: Systems, methods, and computer programs are disclosed for scheduling volatile memory maintenance events. One embodiment is a method comprising: a memory controller determining a time-of-service (ToS) window for executing a maintenance event for a volatile memory device coupled to the memory controller via a memory data interface; the memory controller providing a signal to each of a plurality of processors on a system on chip (SoC) for scheduling the maintenance event; each of the plurality of processors independently generating in response to the signal a corresponding schedule notification for the maintenance event; and the memory controller determining when to execute the maintenance event in response to receiving one or more of the schedule notifications generated by the plurality of processors and based on a processor priority scheme.

公开(公告)号：WO2015094820A2

公开(公告)日：2015-06-25

申请号：PCT/US2014/069380

申请日：2014-12-09

Applicant: QUALCOMM INCORPORATED

Inventor： ANDERSON, Jon James ,  STEWART, Richard Alan

IPC: G06F9/50

CPC classification number: G06F9/5094 ,  G06F9/505 ,  G06F9/5066 ,  G06F9/5077

Abstract: Aspects include computing devices, systems, and methods for adjusting the assignment of tasks to processor cores in a multi-core processing system to increase operating life and maximize device performance by wear-leveling the processor cores. A reliability engine may be configured to collect operation or built in self test data of thermal output and current leakage, and historical operation time for a group of equivalent processor cores configured for the same purpose. Collected data may be applied to a weighted function to determine priorities for each equivalent processor core in the group. The reliability engine may rearrange a virtual processor identification translation table according to the priorities of the equivalent processor cores. A high level operating system may issue a process request specifying a processor core and the specified processor core may be translated to a different processor core according to the order of processor cores dictated by the priorities.

Abstract translation: 方面包括用于调整多核处理系统中的处理器核的任务分配的计算设备，系统和方法，以通过损耗均衡处理器核来延长工作寿命和最大化设备性能。 可靠性引擎可以被配置为收集操作或内置热输出和电流泄漏的自测数据以及针对配置用于相同目的的一组等同处理器核心的历史操作时间。 收集到的数据可以应用于加权函数，以确定组中每个等效处理器内核的优先级。 可靠性引擎可以根据等效处理器核的优先级重新排列虚拟处理器标识转换表。 高级操作系统可以发出指定处理器核心的处理请求，并且指定的处理器核心可以根据由优先级指示的处理器核心的顺序被转换为不同的处理器核心。

公开(公告)号：WO2016126447A1

公开(公告)日：2016-08-11

申请号：PCT/US2016/014699

申请日：2016-01-25

Applicant: QUALCOMM INCORPORATED

Inventor： STEWART, Richard Alan

IPC: G06F1/20 ,  G11C7/04 ,  G06F9/50 ,  H01L23/34

CPC classification number: G06F1/206 ,  G05B13/021 ,  G06F9/5094 ,  G11C7/04 ,  G11C29/028 ,  G11C2207/2254

Abstract: Various embodiments of methods and systems for calibration margin optimization of a target component in a portable computing device are disclosed. Because calibration of certain components is most optimally implemented when the component is at a certain operating temperature, or a series of certain operating temperatures, embodiments of the solution leverage thermal energy generation capabilities of nearby components to manage the operating temperature of a target component to be calibrated.

Abstract translation: 公开了用于便携式计算设备中的目标组件的校准余量优化的方法和系统的各种实施例。 因为某些组件的校准在组件处于某一工作温度或一系列某些工作温度时最佳地实现，因此该解决方案的实施例利用附近组件的热能产生能力来管理目标组件的工作温度 校准。

公开(公告)号：WO2016069109A1

公开(公告)日：2016-05-06

申请号：PCT/US2015/048315

申请日：2015-09-03

Applicant: QUALCOMM INCORPORATED

Inventor： OPORTUS VALENZUELA, Andres Alejandro ,  SENIOR, Richard ,  RAGHAVENDRA, Raghuveer ,  GENG, Nieyan ,  CHHABRA, Gurvinder Singh ,  STEWART, Richard Alan

IPC: H03M7/30 ,  G06F12/08

CPC classification number: G06F3/0608 ,  G06F3/064 ,  G06F3/0646 ,  G06F3/0673 ,  G06F12/08 ,  G06F2212/401 ,  H03M7/30

Abstract: Aspects include computing devices, systems, and methods for implementing executing decompression of a compressed page. A computing device may determine a decompression block belonging to a compressed page that contains a code instruction requested in a memory access request. Decompression blocks, other than the decompression block containing the requested code instruction, may be selected for decompression based on their locality with respect to the decompression block containing the requested code instruction. Decompression blocks not identified for decompression may be substituted for a fault or exception code. The computing device may decompress decompression blocks identified for decompression, terminating the decompression of the compressed page upon filling all blocks with decompressed blocks, faults, or exception code. The remaining decompression blocks belonging to the compressed page may be decompressed after or concurrently with the execution of the requested code instruction.

Abstract translation: 方面包括用于实现压缩页面的执行解压缩的计算设备，系统和方法。 计算设备可以确定属于压缩页面的解压缩块，其包含在存储器访问请求中请求的代码指令。 根据包含所请求的代码指令的解压缩块的位置，可以选择解压缩块（除了包含请求的代码指令的解压缩块）以进行解压缩。 未被解压缩的解压缩块可能代替故障或异常代码。 计算设备可以解压缩被解压缩的解压缩块，在用解压缩块，故障或异常代码填充所有块时终止压缩页面的解压缩。 属于压缩页面的剩余解压缩块可以在执行所请求的代码指令之后或同时执行解压缩。

公开(公告)号：WO2018190989A1

公开(公告)日：2018-10-18

申请号：PCT/US2018/023254

申请日：2018-03-20

Applicant: QUALCOMM INCORPORATED

Inventor： ANDERSON, Jon James ,  STEWART, Richard Alan ,  MERRIKH, Ali Akbar ,  PLATT, Chris ,  YEAGER, Hans Lee ,  WELLS, Ryan Donovan

IPC: G06F9/48 ,  G06F9/50

CPC classification number: G06F9/4893 ,  G06F9/5044 ,  Y02D10/24

Abstract: Aspects include computing devices, systems, and methods for managing a first computing device component of a computing device in order to extend an operating life of the computing device component. In an aspect, a processing device may determine a condition estimator of the first computing device component, determine whether the condition estimator of the first computing device component indicates that a condition of the first computing device component is worse than the condition of a second computing device component, and assign workloads to the first and second computing device components to balance deterioration of the condition of the first and second computing device components in response to determining that the condition estimator of the first computing device component indicates that the condition of the first computing device component is worse than the condition of the second computing device component.

公开(公告)号：WO2010127005A1

公开(公告)日：2010-11-04

申请号：PCT/US2010/032771

申请日：2010-04-28

Applicant: QUALCOMM Incorporated ,  STEWART, Richard Alan

Inventor： STEWART, Richard Alan

IPC: G06F11/36 ,  G06F21/00

CPC classification number: G06F8/75 ,  G06F2221/2105

Abstract: Methods and computing devices enable identifying particular software functions, modules or arithmetic blocks within a software binary image. Memory register and memory address references within the binary image are normalized. Functions within the binary image are identified. Each function within the binary image is compared against one or more reference function binary images to determine if there is a match. The function-to-reference function comparison may be accomplished by comparing bit patterns or by comparing hash values generated by applying a hash function to the selected function and the reference function. Component parts within functions in the binary image can be identified and compared to reference function component parts within a reference function or within a database of reference function component parts. Results of the comparisons may be used to determine a degree to which the software binary image matches reference functions and/or component parts.

Abstract translation: 方法和计算设备能够识别软件二进制图像内的特定软件功能，模块或算术块。 二进制图像内的存储器寄存器和存储器地址引用被归一化。 识别二进制图像内的功能。 二进制图像中的每个函数与一个或多个参考函数二进制图像进行比较，以确定是否存在匹配。 功能对参考功能比较可以通过比较比特模式或通过将通过将哈希函数应用于所选择的功能和参考功能而生成的散列值来实现。 可以识别二进制图像中函数内的组成部分，并将其与引用函数中的引用函数组件部分或参考函数组件数据库进行比较。 可以使用比较结果来确定软件二进制图像与参考功能和/或组件部分匹配的程度。

公开(公告)号：WO2018217289A1

公开(公告)日：2018-11-29

申请号：PCT/US2018/024382

申请日：2018-03-26

Applicant: QUALCOMM INCORPORATED

Inventor： CHUN, Dexter Tamio ,  STEWART, Richard Alan

IPC: G06F13/16 ,  G06F1/32

CPC classification number: G06F1/08 ,  G06F1/324 ,  G06F1/3275 ,  G06F3/0611 ,  G06F3/0629 ,  G06F3/0683 ,  G06F13/1689

Abstract: Pipelined logic latency in a memory system operating at a reduced frequency may be compensated for. Pipelined logic may be controlled using at least first and second clock signals. All registers of the pipelined logic may be controlled using the first clock signal when the memory system is operating at a higher frequency. However, when the memory system is operating at a reduced frequency, one or more registers may be controlled using the first clock signal, and one or more other registers may be controlled using the second clock signal.

公开(公告)号：WO2017007551A1

公开(公告)日：2017-01-12

申请号：PCT/US2016/035658

申请日：2016-06-03

Applicant: QUALCOMM INCORPORATED

Inventor： STEWART, Richard Alan ,  CHUN, Dexter Tamio

IPC: G06F11/10

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/1044 ,  G06F11/1072 ,  G06F12/0246

Abstract: Systems, methods, and computer programs are disclosed for providing error detection or correction with flash cell mapping. One embodiment is a method comprising generating raw page data for a physical page in a main array of a flash memory device. The raw page data comprises less than a capacity of the physical page generated using a non-power-of-two flash cell mapping. One or more parity bits are generated for the raw page data using an error detection or correction scheme. The method stores the raw page data and the one or more parity bits in the physical page in the main array.

Abstract translation: 公开了用于提供具有闪存单元映射的错误检测或校正的系统，方法和计算机程序。 一个实施例是一种方法，包括为闪存设备的主阵列中的物理页生成原始页数据。 原始页面数据包括使用非二功能闪存单元映射生成的物理页面的容量小于该容量。 使用错误检测或校正方案为原始页数据生成一个或多个奇偶校验位。 该方法将原始页面数据和一个或多个奇偶校验位存储在主阵列中的物理页面中。

公开(公告)号：WO2016130440A1

公开(公告)日：2016-08-18

申请号：PCT/US2016/016876

申请日：2016-02-05

Applicant: QUALCOMM INCORPORATED

Inventor： CHUN, Dexter Tamio ,  LI, Yanru ,  STEWART, Richard Alan ,  DE, Subrato Kumar

IPC: G06F13/16

CPC classification number: G06F13/26 ,  G06F13/1636 ,  G06F13/1663 ,  G06F13/18

Abstract: Systems, methods, and computer programs are disclosed for scheduling volatile memory maintenance events. One embodiment is a method comprising: a memory controller determining a time-of-service (ToS) window for executing a maintenance event for a volatile memory device coupled to the memory controller via a memory data interface; the memory controller providing a signal to each of a plurality of processors on a system on chip (SoC) for scheduling the maintenance event; each of the plurality of processors independently generating in response to the signal a corresponding schedule notification for the maintenance event; and the memory controller determining when to execute the maintenance event in response to receiving one or more of the schedule notifications generated by the plurality of processors and based on a processor priority scheme.

Abstract translation: 公开了用于调度易失性存储器维护事件的系统，方法和计算机程序。 一个实施例是一种方法，包括：存储器控制器，其确定用于经由存储器数据接口耦合到存储器控制器的易失性存储器设备执行维护事件的服务时间（ToS）窗口; 所述存储器控制器为片上系统（SoC）上的多个处理器中的每一个提供信号，用于调度所述维护事件; 所述多个处理器中的每一个独立地响应于所述信号产生用于所述维护事件的对应的调度通知; 并且所述存储器控制器响应于接收到由所述多个处理器产生的所述调度通知中的一个或多个并且基于处理器优先级方案来确定何时执行所述维护事件。