公开(公告)号：WO2003073726A2

公开(公告)日：2003-09-04

申请号：PCT/US2003/006330

申请日：2003-02-27

Applicant: QUALCOMM INCORPORATED

Inventor： ABROL, Nischal ,  LIN, Jian ,  PAN, Hanfang ,  TURNER, Simon

IPC: H04L29/06

CPC classification number: H04L69/08 ,  H04L69/16 ,  H04L69/168 ,  H04L69/324

Abstract: An HDLC accelerator includes a deframer and framer to respectively accelerate the deframing and framing processes for PPP packets. The deframer includes an input interface unit, a detection unit, a conversion unit, and an output interface unit. The input interface unit receives a packet of data to be deframed. The detection unit evaluates each data byte to detect for special bytes (e.g., flag, escape, and invalid bytes). The conversion unit deframes the received data by removing flag and escape bytes, "un-escaping" the data byte following each escape byte, providing a header word for each flag byte, and checking each deframed packet based on a frame check sequence (FCS) value associated with the packet. The output interface unit provides deframed data and may further perform byte alignment in providing the deframed data. A state control unit provides control signals indicative of specific tasks to be performed for deframing.

Abstract translation: HDLC加速器包括一个除帧和帧分频器，以分别加速PPP报文的去帧和成帧过程。 除法器包括输入接口单元，检测单元，转换单元和输出接口单元。 输入接口单元接收要解帧的数据包。 检测单元评估每个数据字节以检测特殊字节（例如，标志，转义和无效字节）。 转换单元通过删除标志和转义字节来去除所接收的数据，“解除”每个转义字节后面的数据字节，为每个标志字节提供标题字，并且基于帧校验序列（FCS）检查每个失真的分组， 值与数据包相关联。 输出接口单元提供去数据，并且可以在提供失真数据时进一步执行字节对齐。 状态控制单元提供指示要执行的特定任务的控制信号。

公开(公告)号：WO2003073726A3

公开(公告)日：2003-09-04

申请号：PCT/US2003/006330

申请日：2003-02-27

Applicant: QUALCOMM INCORPORATED

Inventor： ABROL, Nischal ,  LIN, Jian ,  PAN, Hanfang ,  TURNER, Simon

IPC: H04L29/06

Abstract: An HDLC accelerator includes a deframer and framer to respectively accelerate the deframing and framing processes for PPP packets. The deframer includes an input interface unit, a detection unit, a conversion unit, and an output interface unit. The input interface unit receives a packet of data to be deframed. The detection unit evaluates each data byte to detect for special bytes (e.g., flag, escape, and invalid bytes). The conversion unit deframes the received data by removing flag and escape bytes, "un-escaping" the data byte following each escape byte, providing a header word for each flag byte, and checking each deframed packet based on a frame check sequence (FCS) value associated with the packet. The output interface unit provides deframed data and may further perform byte alignment in providing the deframed data. A state control unit provides control signals indicative of specific tasks to be performed for deframing.

公开(公告)号：WO2015156973A1

公开(公告)日：2015-10-15

申请号：PCT/US2015/021260

申请日：2015-03-18

Applicant: QUALCOMM INCORPORATED

Inventor： LIN, Jian ,  KANG, Insung ,  WANG, Shanshan

IPC: H04L1/18

CPC classification number: H04W28/0278 ,  H04L1/1835 ,  H04L1/1854 ,  H04W72/0406

Abstract: Systems, methods and apparatus for wireless communication are provided. In one aspect, the method comprises receiving at least one downlink packet. The method further comprises generating an acknowledge message in response to receiving the at least one downlink packet. The method further comprises prioritizing the acknowledge message in a buffer according to a probability, the probability based at least in part on a current utilization level of the buffer. The method may further comprise one or more of the following: setting the probability to a first value when the utilization level is below a first level, setting the probability to a second value when the utilization level is above the first level and below a second level, and setting the probability to a third value when the utilization level is above the second level. The second value may be adjusted based on feedback corresponding to a downlink throughput.

Abstract translation: 提供了用于无线通信的系统，方法和装置。 一方面，该方法包括接收至少一个下行链路分组。 所述方法还包括响应于接收所述至少一个下行链路分组而生成确认消息。 该方法还包括根据概率将缓存器中的确认消息优先化，该概率至少部分地基于缓冲器的当前利用水平。 该方法还可以包括以下中的一个或多个：当利用水平低于第一水平时将概率设置为第一值，当利用水平高于第一水平并低于第二水平时​​将概率设置为第二值 ，并且当利用水平高于第二水平时​​将概率设置为第三值。 可以基于对应于下行链路吞吐量的反馈来调整第二值。

公开(公告)号：WO2003023627A1

公开(公告)日：2003-03-20

申请号：PCT/US2002/028677

申请日：2002-09-10

Applicant: QUALCOMM INCORPORATED

Inventor： TURNER, Simon ,  KING, Scott ,  LIN, Jian ,  TAYLOR, Kerry

IPC: G06F13/40

CPC classification number: G06F13/4013

Abstract: A method and system for transferring data bytes includes a first memory adapted to store a plurality of multiple-byte data words including header field bytes and one or more data field bytes. The system also includes a second memory adapted to store data field bytes transferred thereto from the first memory. A controller coupled to the first and second memories reads a data word including the header field byte and the one or more data field bytes out of the first memory. The system also includes a data packer coupled to the controller and the second memory. The controller and data packer cooperate to transfer the one or more data field bytes of the first data word read from the first memory to the second memory. The data packer stores only the one or more data field bytes in the second memory contiguously with a previously transferred and stored data field byte.

Abstract translation: 用于传送数据字节的方法和系统包括适于存储包括头字段字节和一个或多个数据字段字节的多个多字节数据字的第一存储器。 该系统还包括适于存储从第一存储器传送到其中的数据字段字节的第二存储器。 耦合到第一和第二存储器的控制器从第一存储器读出包括报头字段字节和一个或多个数据字段字节的数据字。 该系统还包括耦合到控制器和第二存储器的数据封装器。 控制器和数据封装器协作将从第一存储器读取的第一数据字的一个或多个数据字段字节传送到第二存储器。 数据打包器仅将第二存储器中的一个或多个数据字段字节与先前传送和存储的数据字节字节连续存储。

公开(公告)号：EP1264411A2

公开(公告)日：2002-12-11

申请号：EP01916349.2

申请日：2001-03-02

Applicant: QUALCOMM INCORPORATED

Inventor： YOUNIS, Saed ,  SIMIC, Emilija ,  WILBORN, Thomas ,  ZHANG, Haitao ,  FILIPOVIC, Daniel ,  KAUFMAN, Ralph ,  LIN, Jian

IPC: H04B1/00

CPC classification number: H03G3/3042 ,  H03F2203/7239 ,  H03G1/0088

Abstract: Transmitter architectures for a communications system having improved performance over conventional transmitter architectures. The improvements include a combination of the following: faster response time for the control signals, improved linearity, reduced interference, reduced power consumption, lower circuit complexity, and lower costs. For a cellular application, these improvements can lead to increased system capacity, smaller telephone size, increased talk and standby times, and greater acceptance of the product. Circuitry is provided to speed up the response time of a control signal. The control loop for various elements in the transmit signal path are integrated. A gain control mechanism allows for accurate adjustment of the output transmit power level. Control mechanisms are provided to power down the power amplifier, or th e entire transmit signal path, when not needed. The gains of the various elements in the transmit signal path are controlled to reduce transients in the output transmit power, and to also ensure that transients are downward.

公开(公告)号：EP1479210B1

公开(公告)日：2015-12-30

申请号：EP03713826.0

申请日：2003-02-27

Applicant: QUALCOMM INCORPORATED

Inventor： ABROL, Nischal ,  LIN, Jian ,  PAN, Hanfang ,  TURNER, Simon

IPC: H04L29/06 ,  H04L29/08

CPC classification number: H04L69/08 ,  H04L69/16 ,  H04L69/168 ,  H04L69/324

公开(公告)号：EP1066559A1

公开(公告)日：2001-01-10

申请号：EP99911150.3

申请日：1999-03-04

Applicant: QUALCOMM Incorporated

Inventor： SIH, Gilbert, C. ,  ZOU, Quizhen ,  JHA, Sanjay, K. ,  KANG, Inyup ,  LIN, Jian ,  MOTIWALA, Quaeed ,  JOHN, Deepu ,  ZHANG, Li ,  ZHANG, Haitao ,  LEE, Way-Shing ,  SAKAMAKI, Charles, E. ,  KANTAK, Prashant, A.

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F12/0886 ,  G06F9/30036 ,  G06F9/30105 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/30141 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/3816 ,  G06F9/3885 ,  G06F9/3893 ,  G06F15/7807

Abstract: A circuit for digital signal processing calls for the use of a variable length instruction set. An exemplary DSP includes a set of three data buses (108, 110, 112) over which data may be exchanged with a register bank (120) and three data memories (102, 103, 104). A register bank (120) may be used that has registers accessible by at least two processing units (128, 130). An instruction fetch unit (156) may be included that receives instructions of variable length stored in an instruction memory (152). The instruction memory (152) may be separate from the set of three data memories (102, 103, 104).

公开(公告)号：EP1264411B1

公开(公告)日：2009-11-11

申请号：EP01916349.2

申请日：2001-03-02

Applicant: QUALCOMM INCORPORATED

Inventor： YOUNIS, Saed ,  SIMIC, Emilija ,  WILBORN, Thomas ,  ZHANG, Haitao ,  FILIPOVIC, Daniel ,  KAUFMAN, Ralph ,  LIN, Jian

IPC: H04B1/00

CPC classification number: H03G3/3042 ,  H03F2203/7239 ,  H03G1/0088

Abstract: Transmitter architectures for a communications system having improved performance over conventional transmitter architectures. The improvements include a combination of the following: faster response time for the control signals, improved linearity, reduced interference, reduced power consumption, lower circuit complexity, and lower costs. For a cellular application, these improvements can lead to increased system capacity, smaller telephone size, increased talk and standby times, and greater acceptance of the product. Circuitry is provided to speed up the response time of a control signal. The control loop for various elements in the transmit signal path are integrated. A gain control mechanism allows for accurate adjustment of the output transmit power level. Control mechanisms are provided to power down the power amplifier, or th e entire transmit signal path, when not needed. The gains of the various elements in the transmit signal path are controlled to reduce transients in the output transmit power, and to also ensure that transients are downward.

公开(公告)号：EP1066559B1

公开(公告)日：2005-06-08

申请号：EP99911150.3

申请日：1999-03-04

Applicant: QUALCOMM INCORPORATED

Inventor： SIH, Gilbert, C. ,  ZOU, Quizhen ,  JHA, Sanjay, K. ,  KANG, Inyup ,  LIN, Jian ,  MOTIWALA, Quaeed ,  JOHN, Deepu ,  ZHANG, Li ,  ZHANG, Haitao ,  LEE, Way-Shing ,  SAKAMAKI, Charles, E. ,  KANTAK, Prashant, A.

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F12/0886 ,  G06F9/30036 ,  G06F9/30105 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/30141 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/3816 ,  G06F9/3885 ,  G06F9/3893 ,  G06F15/7807

公开(公告)号：EP1479210A2

公开(公告)日：2004-11-24

申请号：EP03713826.0

申请日：2003-02-27

Applicant: QUALCOMM Incorporated

Inventor： ABROL, Nischal ,  LIN, Jian ,  PAN, Hanfang ,  TURNER, Simon

IPC: H04L29/06 ,  H04L29/08

CPC classification number: H04L69/08 ,  H04L69/16 ,  H04L69/168 ,  H04L69/324

Abstract: An HDLC accelerator includes a deframer and framer to respectively accelerate the deframing and framing processes for PPP packets. The deframer includes an input interface unit, a detection unit, a conversion unit, and an output interface unit. The input interface unit receives a packet of data to be deframed. The detection unit evaluates each data byte to detect for special bytes (e.g., flag, escape, and invalid bytes). The conversion unit deframes the received data by removing flag and escape bytes, 'un-escaping' the data byte following each escape byte, providing a header word for each flag byte, and checking each deframed packet based on a frame check sequence (FCS) value associated with the packet. The output interface unit provides deframed data and may further perform byte alignment in providing the deframed data. A state control unit provides control signals indicative of specific tasks to be performed for deframing.