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    TRANSISTOR WITH LOW RESISTIVITY CARBON ALLOY
    1.
    发明申请
    TRANSISTOR WITH LOW RESISTIVITY CARBON ALLOY 审中-公开

    公开(公告)号：WO2018217570A1

    公开(公告)日：2018-11-29

    申请号：PCT/US2018/033405

    申请日：2018-05-18

    Applicant: QUALCOMM INCORPORATED

    Inventor： LU, Ye ,  BAO, Junjing ,  YANG, Bin ,  GE, Lixin ,  YUE, Yun

    IPC: H01L29/49 ,  H01L29/78 ,  H01L29/66

    Abstract: A complementary metal-oxide-semiconductor (CMOS) transistor may include a first semiconductor structure and a gate stack on the first semiconductor structure. The gate stack may include a gate dielectric layer on the first semiconductor structure, a work function material on the gate dielectric layer, and a gate metal fill material on the work function material of the gate stack. The gate metal fill material may include a low resistivity carbon alloy. A dielectric fill material may be included on the gate stack.

    MULTI-BIT COMPUTE-IN-MEMORY (CIM) ARRAYS EMPLOYING BIT CELL CIRCUITS OPTIMIZED FOR ACCURACY AND POWER EFFICIENCY
    4.
    发明申请
    MULTI-BIT COMPUTE-IN-MEMORY (CIM) ARRAYS EMPLOYING BIT CELL CIRCUITS OPTIMIZED FOR ACCURACY AND POWER EFFICIENCY 审中-公开

    公开(公告)号：WO2021225716A1

    公开(公告)日：2021-11-11

    申请号：PCT/US2021/024558

    申请日：2021-03-29

    Applicant: QUALCOMM INCORPORATED

    Inventor： LU, Ye ,  WANG, Zhongze ,  CHIDAMBARAM, Periannan

    IPC: G11C11/54 ,  G11C5/02 ,  G11C7/10 ,  G11C11/412 ,  G11C11/417 ,  G06G7/163 ,  G06N3/063

    Abstract: A bit cell circuit of a most-significant bit (MSB) of a multi-bit product generated in an array of bit cells in a compute-in-memory (CIM) array circuit is configured to receive a higher supply voltage than a supply voltage provided to a bit cell circuit of another bit cell corresponding to another bit of the multi-bit product. A bit cell circuit receiving a higher supply voltage increases a voltage difference between increments of an accumulated voltage, which can increase accuracy of an analog-to-digital converter determining a pop-count. A bit cell circuit of the MSB in the CIM array circuit receives the higher supply voltage to increase accuracy of the MSB which increases accuracy of the CIM array circuit output. A capacitance of a capacitor in the bit cell circuit of the MSB is smaller to avoid an increase in energy consumption due to the higher voltage.

    GATE CUT LAST PROCESSING WITH SELF-ALIGNED SPACER
    5.
    发明申请
    GATE CUT LAST PROCESSING WITH SELF-ALIGNED SPACER 审中-公开

    公开(公告)号：WO2020023144A1

    公开(公告)日：2020-01-30

    申请号：PCT/US2019/038044

    申请日：2019-06-19

    Applicant: QUALCOMM INCORPORATED

    Inventor： LU, Ye ,  YANG, Haining

    IPC: H01L27/088 ,  H01L21/8234

    Abstract: A fin field effect transistors (FinFET) array includes a first transistor having a fin and a first conductive gate on the fin. The FinFET array also includes a second transistor having another fin and a second conductive gate on the other fin. The FinFET array further includes a first dielectric material and a self-aligned dielectric spacer. The first dielectric material is between the first transistor and the second transistor and on at least a portion of sidewalls of each of the first conductive gate and the second conductive gate. The self-aligned dielectric spacer is on at least a portion of the sidewalls of each of the first conductive gate and the second conductive gate.

    MIDDLE-OF-LINE SHIELDED GATE FOR INTEGRATED CIRCUITS
    6.
    发明申请
    MIDDLE-OF-LINE SHIELDED GATE FOR INTEGRATED CIRCUITS 审中-公开

    公开(公告)号：WO2019070346A1

    公开(公告)日：2019-04-11

    申请号：PCT/US2018/047173

    申请日：2018-08-21

    Applicant: QUALCOMM INCORPORATED

    Inventor： GE, Lixin ,  YANG, Bin ,  LU, Ye ,  BAO, Junjing ,  CHIDAMBARAM, Periannan

    IPC: H01L23/522 ,  H01L27/06 ,  H01L27/088

    Abstract: Middle-of-line (MOL) shielded gate in integrated circuits (ICs) are disclosed. One or more metal resistors are fabricated in a MOL layer in the IC to reduce gate to drain parasitic capacitance in the semiconductor area. By fabricating a metal resistor in the MOL layer, the metal resistor can be localized close to semiconductor devices to more effectively reduce parasitic capacitance of the semiconductor devices without adding costs or defects to the current fabrication processes. The current fabrication processes may be used to create contacts in the MOL to fabricate the metal resistor.

    MULTI-GATE HIGH ELECTRON MOBILITY TRANSISTORS (HEMTS) EMPLOYING TUNED RECESS DEPTH GATES FOR IMPROVED DEVICE LINEARITY
    10.
    发明申请
    MULTI-GATE HIGH ELECTRON MOBILITY TRANSISTORS (HEMTS) EMPLOYING TUNED RECESS DEPTH GATES FOR IMPROVED DEVICE LINEARITY 审中-公开

    公开(公告)号：WO2021207485A1

    公开(公告)日：2021-10-14

    申请号：PCT/US2021/026366

    申请日：2021-04-08

    Applicant: QUALCOMM INCORPORATED

    Inventor： TANG, Chenjie ,  LU, Ye ,  FENG, Peijie ,  BAO, Junjing

    IPC: H01L29/778 ,  H01L29/20 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66

    Abstract: A multi-gate HEMT includes at least two gates (202, 204), with at least one (204) recessed the same depth or at a deeper depth in a barrier layer (206) than at least one other gate (202). Recessing a gate decreases the thickness of the barrier layer (206) beneath the gate, reducing a density of high mobility carriers in a two- dimensional electron gas layer (2DEG) conductive channel formed at the heterojunction of a barrier layer (206) and a buffer layer (210) below the recessed gate (204). The recessed gate can increase gate control of the 2DEG conductive channel. The multi-gate HEMT has at least one gate recessed the same depth or a deeper depth into the buffer layer than another gate, which forms at least two different turn-on voltages for different gates. This can achieve improvement of transconductance linearity and a positive shift of the threshold voltage.

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