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    THREE DIMENSIONAL (3D) DOUBLE GATE SEMICONDUCTOR
    1.
    发明申请
    THREE DIMENSIONAL (3D) DOUBLE GATE SEMICONDUCTOR 审中-公开

    公开(公告)号：WO2023283500A1

    公开(公告)日：2023-01-12

    申请号：PCT/US2022/071943

    申请日：2022-04-27

    Applicant: QUALCOMM INCORPORATED

    Inventor： LI, Xia ,  YANG, Bin ,  BAO, Junjing

    IPC: H01L29/778 ,  H01L29/06 ,  H01L27/06 ,  H01L29/24 ,  H01L29/423 ,  H01L21/336 ,  H01L29/786 ,  H01L29/51

    Abstract: Disclosed are semiconductor devices including a double gate metal oxide semiconductor (MOS) transistor and methods for fabricating the same. The double gate MOS transistor includes a first back gate, a second back gate, and a first dielectric layer disposed on the first back gate and on the second back gate. An MX2 material layer is disposed on the first dielectric layer, a second dielectric layer disposed on the MX2 material layer, and a work function metal (WFM) is disposed on the second dielectric layer. A front gate is disposed on the WFM, which fills a space between the first back gate and the second back.

    MULTIPLE BIT MAGNORESISTIVE RANDOM ACCESS MEMORY CELL
    2.
    发明申请
    MULTIPLE BIT MAGNORESISTIVE RANDOM ACCESS MEMORY CELL 审中-公开

    公开(公告)号：WO2022236205A1

    公开(公告)日：2022-11-10

    申请号：PCT/US2022/071322

    申请日：2022-03-24

    Applicant: QUALCOMM INCORPORATED

    Inventor： LI, Xia ,  YANG, Bin

    IPC: G11C11/16 ,  G11C11/56

    Abstract: Disclosed are examples of multiple bit magnetoresistive random access memory (MRAM) cells. A multiple bit MRAM cell may comprise a fixed layer, alternately stacked N tunnel barriers and N free layers, and a tunnel cap. N, which may represent number of bits of the MRAM cell, may be greater than or equal to two. Magnetic moment of the fixed layer may be fixed in one perpendicular direction. Magnetic moments of the free layers may be switchable from one to other perpendicular directions upon application of switch currents. The switch currents may be different for different layers. The magnetic moments of the free layers may be switched separately or otherwise independently of other free layers when the switch currents are applied separately.

    GALLIUM NITRIDE HIGH ELECTRON MOBILITY TRANSISTOR WITH LEDGES AND FIELD PLATES
    4.
    发明申请
    GALLIUM NITRIDE HIGH ELECTRON MOBILITY TRANSISTOR WITH LEDGES AND FIELD PLATES 审中-公开

    公开(公告)号：WO2020033038A1

    公开(公告)日：2020-02-13

    申请号：PCT/US2019/036310

    申请日：2019-06-10

    Applicant: QUALCOMM INCORPORATED

    Inventor： TAO, Gengming ,  YANG, Bin ,  LI, Xia

    IPC: H01L29/778 ,  H01L29/40 ,  H01L29/06 ,  H01L29/36 ,  H01L29/20

    Abstract: Certain aspects of the present disclosure provide a high electron mobility transistor (HEMT). The HEMT generally includes a gallium nitride (GaN) layer (206) and an aluminum gallium nitride (AIGaN) layer (208) disposed above the GaN layer. The HEMT also includes a source electrode (210), a gate electrode (212), and a drain electrode (214) disposed above the AIGaN layer. The HEMT further includes n- doped protuberance(s) (240A, 240B) disposed above the AIGaN layer and disposed between at least one of: the gate electrode and the drain electrode; or the source electrode and the gate electrode. Each of the n-doped protuberances is separated from the gate electrode, the drain electrode, and the source electrode.

    SILICON ON INSULATOR (SOI) TRANSCAP DEVICE PROVIDING FRONT AND BACK GATE CAPACITANCE TUNING
    5.
    发明申请
    SILICON ON INSULATOR (SOI) TRANSCAP DEVICE PROVIDING FRONT AND BACK GATE CAPACITANCE TUNING 审中-公开

    公开(公告)号：WO2019022877A1

    公开(公告)日：2019-01-31

    申请号：PCT/US2018/038916

    申请日：2018-06-22

    Applicant: QUALCOMM INCORPORATED

    Inventor： LI, Xia ,  YANG, Bin ,  TAO, Gengming

    IPC: H01L29/93 ,  H01L29/94 ,  H01L29/06

    CPC classification number: H01L29/94 ,  H01L29/0649 ,  H01L29/66189 ,  H01L29/93

    Abstract: Certain aspects of the present disclosure generally relate to a semiconductor variable capacitor offering at least two types of capacitance tuning, as well as techniques for fabricating the same. For example, a CMOS-compatible silicon on insulator (SOI) process with a buried oxide (BOX) layer may provide a transcap with a front gate (above the BOX layer) and a back gate (beneath the BOX layer). The front gate may offer lower voltage, coarse capacitance tuning, whereas the back gate may offer higher voltage, fine capacitance tuning. By offering both types of capacitance tuning, such transcaps may provide greater capacitance resolution. Several variations of transcaps with front gate and back gate tuning are illustrated and described herein.

    HIGH POWER COMPOUND SEMICONDUCTOR FIELD EFFECT TRANSISTOR DEVICES WITH LOW DOPED DRAIN
    6.
    发明申请
    HIGH POWER COMPOUND SEMICONDUCTOR FIELD EFFECT TRANSISTOR DEVICES WITH LOW DOPED DRAIN 审中-公开

    公开(公告)号：WO2019013873A1

    公开(公告)日：2019-01-17

    申请号：PCT/US2018/034155

    申请日：2018-05-23

    Applicant: QUALCOMM INCORPORATED

    Inventor： YANG, Bin ,  LI, Xia ,  TAO, Gengming ,  CHIDAMBARAM, Periannan

    IPC: H01L29/08 ,  H01L29/66 ,  H01L29/778 ,  H01L29/205

    Abstract: A compound semiconductor field effect transistor including a channel layer (524), a multi-layer epitaxial barrier layer (636, 534b, 638, 534c, 640, 534d) on the channel layer. The channel layer being disposed on a doped buffer layer (622), which is disposed on an un-doped buffer layer (522). The compound semiconductor field effect transistor further includes a gate (1454c) on a first tier (636) of the multi- layer epitaxial barrier layer, and through a space between portions of a second tier of the multi-layer epitaxial barrier layer. The compound semiconductor field effect transistor may further include a body contact (1454) electrically coupled to the doped buffer layer (622)

    TRANSISTOR WITH LOW RESISTIVITY CARBON ALLOY
    7.
    发明申请
    TRANSISTOR WITH LOW RESISTIVITY CARBON ALLOY 审中-公开

    公开(公告)号：WO2018217570A1

    公开(公告)日：2018-11-29

    申请号：PCT/US2018/033405

    申请日：2018-05-18

    Applicant: QUALCOMM INCORPORATED

    Inventor： LU, Ye ,  BAO, Junjing ,  YANG, Bin ,  GE, Lixin ,  YUE, Yun

    IPC: H01L29/49 ,  H01L29/78 ,  H01L29/66

    Abstract: A complementary metal-oxide-semiconductor (CMOS) transistor may include a first semiconductor structure and a gate stack on the first semiconductor structure. The gate stack may include a gate dielectric layer on the first semiconductor structure, a work function material on the gate dielectric layer, and a gate metal fill material on the work function material of the gate stack. The gate metal fill material may include a low resistivity carbon alloy. A dielectric fill material may be included on the gate stack.

    COMPOUND SEMICONDUCTOR FIELD EFFECT TRANSISTOR WITH SELF-ALIGNED GATE
    8.
    发明申请
    COMPOUND SEMICONDUCTOR FIELD EFFECT TRANSISTOR WITH SELF-ALIGNED GATE 审中-公开

    公开(公告)号：WO2018217315A1

    公开(公告)日：2018-11-29

    申请号：PCT/US2018/025909

    申请日：2018-04-03

    Applicant: QUALCOMM INCORPORATED

    Inventor： YANG, Bin ,  LI, Xia ,  TAO, Gengming ,  CHIDAMBARAM, Periannan

    IPC: H01L29/20 ,  H01L29/66 ,  H01L29/778

    Abstract: A compound semiconductor field effect transistor (FET) may include gallium nitride (GaN) and alloy material layers. The compound semiconductor FET may also include a pair of L-shaped contacts on the GaN and alloy material layers. The compound semiconductor FET may also include a pair of gate spacers between the L-shaped contacts and on the GaN and alloy material layers, each of the pair of gate spacers contacting one of the L-shaped contacts. The compound semiconductor FET may further include a base gate between the pair of gate spacers and on the GaN and alloy material layers, in which the pair of L-shaped contacts are self-aligned with the base gate.

    COMPOUND SEMICONDUCTOR TRANSISTOR INTEGRATION WITH HIGH DENSITY CAPACITOR
    9.
    发明申请
    COMPOUND SEMICONDUCTOR TRANSISTOR INTEGRATION WITH HIGH DENSITY CAPACITOR 审中-公开

    公开(公告)号：WO2018190951A1

    公开(公告)日：2018-10-18

    申请号：PCT/US2018/018790

    申请日：2018-02-20

    Applicant: QUALCOMM INCORPORATED

    Inventor： YANG, Bin ,  LI, Xia ,  TAO, Gengming

    IPC: H01L21/8252 ,  H01L23/522 ,  H01L27/06 ,  H01L49/02

    Abstract: A metal-insulator-metal (MIM) capacitor includes a compound semiconductor substrate. The MIM capacitor includes a collector contact layer on the compound semiconductor substrate, a first dielectric layer on the collector contact layer, a conductive electrode layer on the first dielectric layer, and a second dielectric layer on the conductive electrode layer. The MIM capacitor includes a first conductive interconnect on the second dielectric layer, a third dielectric layer on the first conductive interconnect, and a second conductive interconnect on the third dielectric layer. A first capacitive component includes the collector contact layer, the conductive electrode layer, and the first dielectric layer. A second capacitive component includes the first conductive interconnect, the conductive electrode layer and the second dielectric layer. A third capacitive component includes the second conductive interconnect, the first conductive interconnect, and the third dielectric layer. The first, second, and third capacitive components are arranged in parallel with each other.

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