公开(公告)号：WO2008154551A1

公开(公告)日：2008-12-18

申请号：PCT/US2008/066452

申请日：2008-06-10

Applicant: QUALCOMM Incorporated ,  WEI, Jian ,  PYLA, Manojkumar ,  CHEN, Xufeng

Inventor： WEI, Jian ,  PYLA, Manojkumar ,  CHEN, Xufeng

IPC: G06F11/267

CPC classification number: G06F11/2236

Abstract: Techniques for debugging a programmable integrated circuit are described. Embodiments include steps of initiating instruction-cache-misses in the integrated circuit using a remote computer executing a test program; substituting, during an instruction-cache-miss event, instructions in the application program with test instructions provided by the test program; and debugging the integrated circuit based on analysis of its responses to the test instructions. In exemplary applications, such techniques are used for debugging graphics processors of wireless communication system-on-chip devices, among other programmable integrated circuit devices.

Abstract translation: 描述了用于调试可编程集成电路的技术。 实施例包括使用执行测试程序的远程计算机启动集成电路中的指令高速缓存未命中的步骤; 在指令高速缓存未命中事件期间，使用测试程序提供的测试指令代替应用程序中的指令; 并根据其对测试指令的响应分析调试集成电路。 在示例性应用中，这种技术用于调试无线通信片上系统的图形处理器以及其他可编程集成电路器件。

公开(公告)号：WO2008061086A2

公开(公告)日：2008-05-22

申请号：PCT/US2007/084523

申请日：2007-11-13

Applicant: QUALCOMM Incorporated ,  CODRESCU, Lucian ,  ANDERSON, William C. ,  VENKUMAHANTI, Suresh ,  GIANNINI, Louis Achille ,  PYLA, Manojkumar ,  CHEN, Xufeng

Inventor： CODRESCU, Lucian ,  ANDERSON, William C. ,  VENKUMAHANTI, Suresh ,  GIANNINI, Louis Achille ,  PYLA, Manojkumar ,  CHEN, Xufeng

CPC classification number: G06F1/3203 ,  G06F11/362 ,  G06F11/3656

Abstract: Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. A method and system control transferring data between debugging registers and digital signal processor processes in association with a power transition sequence of the digital signal processor. In a digital signal processor, debugging registers associate with the core processor process and the debugging process. Control bits control transferring data among the debugging registers, the core processor process and the debugging process. The control bit prevents transferring data among the debugging registers, the core processor process and the debugging process in the event of a power transition sequence. Control bits also prevent a power transition sequence of the digital signal processor in the event of transferring data among the debugging registers and the core processor process or the debugging process.

Abstract translation: 用于设计和使用数字信号处理器的技术，包括（但不限于）用于处理通信（例如，CDMA）系统中的传输。 一种与数字信号处理器的功率转换序列相关联的在调试寄存器和数字信号处理器处理之间传送数据的方法和系统控制。 在数字信号处理器中，调试寄存器与核心处理器进程和调试过程相关联。 控制位控制在调试寄存器，核心处理器进程和调试过程之间传输数据。 控制位防止在电源转换序列的情况下在调试寄存器，核心处理器进程和调试过程之间传输数据。 在调试寄存器和核心处理器处理或调试过程之间传输数据的情况下，控制位还可以防止数字信号处理器的电源转换序列。

公开(公告)号：EP3605275A1

公开(公告)日：2020-02-05

申请号：EP19199047.2

申请日：2011-08-22

Applicant: QUALCOMM Incorporated

Inventor： CHEN, Xufeng ,  ZHONG, Peixin ,  PYLA, Manojkumar

IPC: G06F1/32 ,  G06F13/24

Abstract: In a particular embodiment, a method of monitoring interrupts during a power down event at a processor includes activating an interrupt monitor to detect interrupts. The method also includes isolating an interrupt controller of the processor from the interrupt monitor, where the interrupt controller shares a power domain with the processor. The method also includes detecting interrupts at the interrupt monitor during a power down time period associated with the power down event.

公开(公告)号：WO2013109683A1

公开(公告)日：2013-07-25

申请号：PCT/US2013/021828

申请日：2013-01-17

Applicant: QUALCOMM INCORPORATED

Inventor： LIN, Jentsung ,  BASSETT, Paul D. ,  PYLA, Manojkumar ,  LESTER,, Robert A. ,  KOOB, Christopher E.

IPC: G11C7/10 ,  G06F5/10

CPC classification number: G11C7/1084 ,  G06F5/10

Abstract: Dual-voltage domain memory buffers, and related systems and methods are disclosed. To reduce area needed for voltage level shifters for voltage level shifting, latch banks are provided in a voltage domain of memory buffer read circuitry, separate from the voltage domain of a write data input to the latch banks. A write data input voltage level shifter is disposed between the write data input and the latch banks to voltage level shift write data on the write data input to the voltage domain of the latch banks. In this manner, voltage level shifters are not required to voltage level shift the latch bank outputs, because the latch banks are in the voltage domain of the memory buffer read circuitry. In this manner, semiconductor area that would otherwise be needed for the voltage level shifters to voltage level shift latch bank outputs is not required.

Abstract translation: 公开了双电压域内存缓冲器以及相关的系统和方法。 为了减少用于电压电平移位的电压电平移位器所需的面积，锁存器组被提供在存储缓冲器读取电路的电压域中，与写入数据输入到锁存器组的电压域分开。 写入数据输入电压电平移位器设置在写入数据输入和锁存器组之间，以输入到锁存器组的电压域的写入数据上的电压电平移位写入数据。 以这种方式，由于锁存器组处于存储器缓冲器读取电路的电压域，电压电平移位器不需要电压电平移位锁存器组输出。 以这种方式，不需要将电压电平移位器需要的电压电平移位锁存器组输出的半导体区域。

公开(公告)号：WO2013025637A1

公开(公告)日：2013-02-21

申请号：PCT/US2012/050641

申请日：2012-08-13

Applicant: QUALCOMM Incorporated ,  KOOB, Christopher Edward ,  LIN, Jen Tsung ,  PYLA, Manojkumar ,  SAINT-LAURENT, Martin

Inventor： KOOB, Christopher Edward ,  LIN, Jen Tsung ,  PYLA, Manojkumar ,  SAINT-LAURENT, Martin

IPC: G06F5/06

CPC classification number: G06F5/06 ,  G06F5/10 ,  G06F5/14 ,  G06F2205/102 ,  G11C5/145

Abstract: According to an embodiment, an apparatus includes a data storage device. Data to be stored in the data storage device is level shifted from a first voltage domain to a second voltage domain prior to being stored within the data storage device. The data storage device is powered by the second voltage domain. The apparatus further includes a circuit that is powered by the second voltage domain and that is responsive to data output by the data storage device.

Abstract translation: 根据实施例，一种装置包括数据存储装置。 要存储在数据存储设备中的数据在被存储在数据存储设备中之前从第一电压域电平移位到第二电压域。 数据存储设备由第二电压域供电。 该装置还包括由第二电压域供电并且响应于数据存储装置输出的数据的电路。

公开(公告)号：WO2008061102A2

公开(公告)日：2008-05-22

申请号：PCT/US2007/084578

申请日：2007-11-13

Applicant: QUALCOMM INCORPORATED ,  CODRESCU, Lucian ,  ANDERSON, William C. ,  VENKUMAHANTI, Suresh ,  GIANNINI, Louis Achille ,  PYLA, Manojkumar ,  CHEN, Xufeng

Inventor： CODRESCU, Lucian ,  ANDERSON, William C. ,  VENKUMAHANTI, Suresh ,  GIANNINI, Louis Achille ,  PYLA, Manojkumar ,  CHEN, Xufeng

IPC: G06F11/36

CPC classification number: G06F11/3656 ,  G06F9/3005

Abstract: Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. The method and system improve software instruction debugging operations by capturing real-time information relating to software execution flow and include and instructions and circuitry for operating a core processor process within a core processor. A non-intrusive debugging process operates within a debugging mechanism of a digital signal processor. Non-intrusively monitoring in real time predetermined aspects of software execution occurs with the core processing process and occurs in real-time on the processor. An embedded trace macrocell records selectable aspects of the non-intrusively monitored software execution and generates at least one breakpoint in response to events arising within the selectable aspects of the non-intrusively monitored software execution. The present disclosure controls aspects of the non-intrusive debugging process in response to at least one breakpoint.

Abstract translation: 用于设计和使用数字信号处理器的技术，包括（但不限于）用于处理通信（例如，CDMA）系统中的传输。 该方法和系统通过捕获与软件执行流有关的实时信息来改进软件指令调试操作，并且包括用于在核心处理器内操作核心处理器过程的指令和电路。 非侵入式调试过程在数字信号处理器的调试机制内运行。 实时非侵入式地监控软件执行的预定方面与核心处理过程一起发生并且在处理器上实时发生。 嵌入式跟踪宏小区记录非侵入式监控的软件执行的可选方面并且响应于在非侵入式监控的软件执行的可选方面内出现的事件而产生至少一个断点。 本公开内容响应于至少一个断点来控制非侵入式调试过程的各个方面。

公开(公告)号：WO2016130241A1

公开(公告)日：2016-08-18

申请号：PCT/US2016/012363

申请日：2016-01-06

Applicant: QUALCOMM INCORPORATED

Inventor： KOOB, Christopher Edward ,  CHEN, Xufeng ,  LESTER, Robert Allan ,  PYLA, Manojkumar ,  ZHONG, Peixin

IPC: G06F1/32 ,  H03K19/00

CPC classification number: G06F1/26 ,  G06F1/3237 ,  G06F1/3287 ,  H03K19/0016 ,  Y02D10/128 ,  Y02D10/171

Abstract: The feature size of semiconductor devices continues to decrease in each new generation. Smaller channel lengths lead to increased leakage currents. To reduce leakage current, some power domains within a device may be powered off (e.g., power collapsed) during periods of inactivity. However, when power is returned to the collapsed domains, circuitry in other power domains may experience significant processing overhead associated with reconfiguring communication channels to the newly powered domains. Provided in the present disclosure are exemplary techniques for isolating power domains to promote flexible power collapse while better managing the processing overhead associated with reestablishing data connections.

Abstract translation: 半导体器件的特征尺寸在每一代新一代继续下降。 较小的通道长度导致泄漏电流增加。 为了减少泄漏电流，在不活动期间，器件内部的一些电源域可能被断电（例如，电源崩溃）。 然而，当电力返回到折叠域时，其他电力域中的电路可能经历与重新配置到新供电域的通信信道相关联的重要处理开销。 在本公开中提供的是用于隔离功率域以促进柔性功率崩溃的示例性技术，同时更好地管理与重新建立数据连接相关联的处理开销。

公开(公告)号：WO2008061105A2

公开(公告)日：2008-05-22

申请号：PCT/US2007/084587

申请日：2007-11-13

Applicant: QUALCOMM INCORPORATED ,  CODRESCU, Lucian ,  ANDERSON, William, C. ,  VENKUMAHANTI, Suresh ,  GIANNINI, Louis, Achille ,  PYLA, Manojkumar ,  CHEN, Xufeng

Inventor： CODRESCU, Lucian ,  ANDERSON, William, C. ,  VENKUMAHANTI, Suresh ,  GIANNINI, Louis, Achille ,  PYLA, Manojkumar ,  CHEN, Xufeng

IPC: G06F11/36

CPC classification number: G06F11/362 ,  G06F11/3656

Abstract: Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. Stuffing instructions in a processing pipeline of a multi-threaded digital signal processor provides for operating a core processor process and a debugging process within a debugging mechanism. Writing a stuff instruction into a debugging process registry and a stuff command in a debugging process command register provides for identifying a predetermined thread of the multi-threaded digital signal processor in which to execute the stuff instruction. The instruction stuffing process issues a debugging process control resume command during a predetermined stage of executing on the predetermined thread and directs the core processor to perform the stuff instruction during the debugging process. The core processor may then execute the stuffed instruction in association with the core processor process and the debugging process.

Abstract translation: 用于设计和使用数字信号处理器的技术，包括（但不限于）用于处理通信（例如，CDMA）系统中的传输。 在多线程数字信号处理器的处理流水线中的填充指令提供了在调试机制内操作核心处理器进程和调试过程。 将填充指令写入调试进程注册表，并且调试进程命令寄存器中的填充命令用于标识执行填充指令的多线程数字信号处理器的预定线程。 指令填充处理在预定线程的预定执行阶段发出调试过程控制恢复命令，并指示核心处理器在调试过程中执行填充指令。 核心处理器然后可以与核心处理器进程和调试过程相关联地执行填充指令。

公开(公告)号：WO2008061067A2

公开(公告)日：2008-05-22

申请号：PCT/US2007/084456

申请日：2007-11-12

Applicant: QUALCOMM Incorporated ,  CODRESCU, Lucian ,  ANDERSON, William C. ,  VENKUMAHANTI, Suresh ,  GIANNINI, Louis Achille ,  PYLA, Manojkumar ,  CHEN, Xufeng

Inventor： CODRESCU, Lucian ,  ANDERSON, William C. ,  VENKUMAHANTI, Suresh ,  GIANNINI, Louis Achille ,  PYLA, Manojkumar ,  CHEN, Xufeng

CPC classification number: G06F9/3005 ,  G06F9/3009 ,  G06F9/3851 ,  G06F11/362

Abstract: Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. The disclosed method and system provide for processing instructions in a multi-threaded process including the use of breakpoint instructions for generating debugging event(s). Generating a debugging event occurs in response to the execution of breakpoint instructions and executes debugging instructions in response to the debugging event. The debugging instructions debug processing instructions in the multi-threaded processor by transitioning at least one or more threads into a debugging mode. The disclosure generates a debugging return for reporting the executing debugging instructions in the subset of the threads of the multi-threaded processor.

Abstract translation: 用于设计和使用数字信号处理器的技术，包括（但不限于）用于处理通信（例如，CDMA）系统中的传输。 所公开的方法和系统提供处理多线程过程中的指令，包括使用断点指令来产生调试事件。 生成调试事件是为了响应断点指令的执行并执行调试指令来响应调试事件。 调试指令通过将至少一个或多个线程转换到调试模式来调试多线程处理器中的处理指令。 本公开生成用于报告多线程处理器的线程的子集中执行的调试指令的调试返回。

公开(公告)号：WO2014004269A3

公开(公告)日：2014-01-03

申请号：PCT/US2013/046966

申请日：2013-06-21

Applicant: QUALCOMM INCORPORATED

Inventor： PYLA, Manojkumar ,  CODRESCU, Lucian

IPC: G06F12/08

Abstract: In a particular embodiment, a method of managing a cache memory includes, responsive to a cache size change command, changing a mode of operation of the cache memory to a write through/no allocate mode. The method also includes processing instructions associated with the cache memory while executing a cache clean operation when the mode of operation of the cache memory is the write through/no allocate mode. The method further includes after completion of the cache clean operation, changing a size of the cache memory and changing the mode of operation of the cache to a mode other than the write through/no allocate mode.