公开(公告)号：WO2017040987A1

公开(公告)日：2017-03-09

申请号：PCT/US2016/050185

申请日：2016-09-02

Applicant: QUALCOMM INCORPORATED

Inventor： SHIN, Hyunsuk ,  KIM, Jung Pill ,  SHACHAM, Assaf

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/0611 ,  G06F3/0613 ,  G06F3/0625 ,  G06F3/0631 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0661 ,  G06F3/0665 ,  G06F3/0673 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/08 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/1044 ,  G06F2212/152 ,  G06F2212/401

Abstract: Aspects disclosed in the detailed description include hardware accelerated storage compression. In one aspect, prior to writing an uncompressed data block to the storage device, a hardware compression accelerator provided in a storage controller compresses the uncompressed data blocks individually into a compressed data block and allocates the compressed data block to a storage data block in the storage device. The hardware compression accelerator then generates a modified logical block address (LBA) to link the uncompressed data block to the compressed data blocks. In another aspect, the hardware compression accelerator locates a compressed data block based on a corresponding modified LBA and decompresses the compressed data block into an uncompressed data block. By performing hardware accelerated storage compression in the storage controller, it is possible to reduce processing overhead associated with traditional software-based compression systems and improve compression control over traditional storage device driven compression systems.

Abstract translation: 在详细描述中公开的方面包括硬件加速存储压缩。 一方面，在将未压缩的数据块写入到存储装置之前，设置在存储控制器中的硬件压缩加速器将未压缩数据块分别压缩为压缩数据块，并将压缩数据块分配给存储器中的存储数据块 设备。 硬件压缩加速器然后生成修改的逻辑块地址（LBA），以将未压缩的数据块链接到压缩的数据块。 在另一方面，硬件压缩加速器基于相应的修改的LBA定位压缩数据块，并将压缩数据块解压缩为未压缩的数据块。 通过在存储控制器中执行硬件加速存储压缩，可以减少与传统的基于软件的压缩系统相关联的处理开销，并改进对传统存储设备驱动的压缩系统的压缩控制。

公开(公告)号：WO2014172124A1

公开(公告)日：2014-10-23

申请号：PCT/US2014/033083

申请日：2014-04-04

Applicant: QUALCOMM INCORPORATED

Inventor： SHACHAM, Assaf

IPC: G06F3/06 ,  G06F21/78 ,  H04L9/06

CPC classification number: G06F21/78 ,  G06F3/0623 ,  G06F3/0658 ,  G06F3/0679 ,  G06F2221/2107

Abstract: Various features pertain to inline encryption and decryption. In one aspect, inline read/write operations are performed by configuring an off-chip storage device to provide parameters to facilitate inline encryption/decryption of data by a host storage controller of a system-on-a-chip (SoC.) The parameters provided by the storage device to the host storage controller include an identifier that is the same for read and write operations for a particular block of data but differs from one block of data to another. The host storage controller employs the parameters as initial vectors to generate encryption keys for use in encrypting/decrypting data. Exemplary read and write operations of the host storage controller and the off-chip storage device are described herein. Examples are also described wherein the parameters are obtained from host memory rather than from the storage device.

Abstract translation: 各种功能涉及内联加密和解密。 在一个方面，通过配置片外存储设备来提供参数以便于由片上系统（SoC）的主机存储控制器进行数据的内联加密/解密来执行内联读/写操作。参数 由存储设备提供给主机存储控制器的标识符包括对于特定数据块的读取和写入操作相同的标识符，但是不同于一个数据块到另一个数据块。 主机存储控制器采用参数作为初始向量来生成用于加密/解密数据的加密密钥。 这里描述了主存储控制器和片外存储设备的示例性的读取和写入操作。 还描述了其中参数是从主机存储器而不是从存储设备获得的示例。

公开(公告)号：EP3044688B1

公开(公告)日：2017-10-18

申请号：EP14772505.5

申请日：2014-09-08

Applicant: Qualcomm Incorporated

Inventor： SHACHAM, Assaf ,  YAHALOM, Tom ,  ZACKS-SHTRAUSS, Aviad

IPC: G06F13/42

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0679 ,  G06F13/4243 ,  G06F2003/0697 ,  G06F2206/1014

公开(公告)号：EP3044688A1

公开(公告)日：2016-07-20

申请号：EP14772505.5

申请日：2014-09-08

Applicant: Qualcomm Incorporated

Inventor： SHACHAM, Assaf ,  YAHALOM, Tom ,  ZACKS-SHTRAUSS, Aviad

IPC: G06F13/42

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0679 ,  G06F13/4243 ,  G06F2003/0697 ,  G06F2206/1014

Abstract: Providing command queuing in embedded memories is provided. In particular, aspects disclosed herein relate to a process through which a status of the queue is communicated to a host from a device. Aspects of the present disclosure use the command structure of the embedded Multi-Media Card (eMMC) standard, such that the host may determine a state of the queue in the device proximate a known end of an in-progress data transfer. In this manner, the host can select a task to commence after completion of a current data transfer while the current data transfer is still ongoing.

Abstract translation: 提供在嵌入式存储器中提供命令排队。 具体地，本文公开的方面涉及将队列的状态从设备传送到主机的过程。 本公开的方面使用嵌入式多媒体卡（eMMC）标准的命令结构，使得主机可以在接近已知的进行中数据传送结束的情况下确定设备中队列的状态。 以这种方式，当当前数据传送仍在进行时，主机可以选择在完成当前数据传输之后开始的任务。

公开(公告)号：WO2015187824A1

公开(公告)日：2015-12-10

申请号：PCT/US2015/033970

申请日：2015-06-03

Applicant: QUALCOMM INCORPORATED

Inventor： SHACHAM, Assaf ,  HAIM, Maya ,  SUSMAN, Lee ,  TEB, David

IPC: G06F13/16

CPC classification number: G06F13/1642 ,  G06F3/06 ,  G06F3/061 ,  G06F3/0664 ,  G06F3/0688 ,  G06F13/16

Abstract: Command trapping in an input/output virtualization (10 V) host controller (HC) (IOV-HC) of a flash-memory-based storage device is disclosed. In one aspect, an 10 V- HC is configured to receive a request from a client register interface (CRI) of one of multiple input/output (I/O) clients. The IOV-HC inspects a content of the request prior to the request being passed to a transport protocol engine. Based on the content, the IOV-HC determines whether the request should be further processed or should be trapped. If the IOV-HC determines that the request should be trapped, the IOV-HC traps the request using a request trap. In some aspects, the IOV-HC generates an interrupt to a virtual machine manager (VMM) to notify the VMM that the request was trapped. In some aspects, the IOV-HC provides a response generation circuit to receive instructions from the VMM to generate a response to the CRI from which the trapped request originated.

Abstract translation: 公开了基于闪存存储器的存储设备的输入/输出虚拟化（10V）主机控制器（HC）（IOV-HC）中的命令捕获。 在一个方面，10V-HC被配置为从多个输入/输出（I / O）客户端之一的客户端寄存器接口（CRI）接收请求。 在请求被传递到传输协议引擎之前，IOV-HC检查请求的内容。 根据内容，IOV-HC确定请求是否应进一步处理或应被捕获。 如果IOV-HC确定请求被捕获，则IOV-HC使用请求陷阱捕获请求。 在某些方面，IOV-HC会向虚拟机管理器（VMM）生成中断，以通知VMM该请求被捕获。 在一些方面，IOV-HC提供响应生成电路以从VMM接收指令以产生对被捕获请求产生的CRI的响应。

公开(公告)号：WO2015187810A1

公开(公告)日：2015-12-10

申请号：PCT/US2015/033953

申请日：2015-06-03

Applicant: QUALCOMM INCORPORATED

Inventor： SHACHAM, Assaf ,  RAVIV, Dolev ,  TEB, David

IPC: G06F13/16 ,  G06F3/06 ,  G11C7/00

CPC classification number: G06F13/16 ,  G06F3/06 ,  G06F3/061 ,  G06F3/0664 ,  G06F3/0688 ,  G11C7/00

Abstract: An input/output virtualization (IOV) host controller (HC) (IOV-HC) of a flash-memory-based storage device is disclosed. In one aspect, an IOV-HC is coupled to input/output (I/O) clients via corresponding client register interfaces (CRIs), and is also coupled to a flash-memory-based storage device. The IOV-HC comprises transfer request list (TRL) slot offset registers indicating slots of a shared TRL that are assigned as base slots to each of the CRIs. The IOV-HC further comprises TRL slot count registers indicating how many slots of the shared TRL are assigned to each of the CRIs. When a transfer request (TR) directed to the flash-memory-based storage device is received from a CRI, the IOV-HC is configured to map the TR to a slot of the shared TRL based on a TRL slot offset register and a TRL slot count register of the plurality of TRL slot count registers corresponding to the CRI.

Abstract translation: 公开了一种基于闪存存储器的存储设备的输入/输出虚拟化（IOV）主机控制器（HC）（IOV-HC）。 在一个方面，IOV-HC通过相应的客户端寄存器接口（CRI）耦合到输入/输出（I / O）客户端，并且还耦合到基于闪存存储器的存储设备。 IOV-HC包括指示被分配为每个CRI的基准时隙的共享TRL的时隙的传送请求列表（TRL）时隙偏移量寄存器。 IOV-HC还包括TRL时隙计数寄存器，其指示共享TRL的多少时隙被分配给每个CRI。 当从CRI接收到指向基于闪速存储器的存储设备的传送请求（TR）时，IOV-HC被配置为基于TRL时隙偏移寄存器和TRL将TR映射到共享TRL的时隙 对应于CRI的多个TRL时隙计数寄存器的时隙计数寄存器。

公开(公告)号：WO2015073768A1

公开(公告)日：2015-05-21

申请号：PCT/US2014/065601

申请日：2014-11-14

Applicant: QUALCOMM INCORPORATED

Inventor： SHACHAM, Assaf ,  GIL, Amit

IPC: G06F13/40

CPC classification number: G06F12/0246 ,  G06F12/0238 ,  G06F13/4068 ,  G06F2212/7207

Abstract: Removable memory card discrimination systems and methods are disclosed. In particular, exemplary embodiments discriminate between secure digital (SD) cards and other removable memory cards that comply with the SD form factor, but support the Universal Flash Storage (UFS) protocol. That is, a host may have a receptacle that supports the SD card form factor and is configured to receive a device. In use, a removable memory card is inserted into the receptacle and, using an SD compliant interrogation signal, the host interrogates a common area on the card so inserted. The common area includes information related to capability descriptors of the card. An SD compliant card will respond with information such as capability descriptors about the SD protocol capabilities, while a UFS compliant card will respond with an indication that the card is UFS compliant. The host may then restart the communication with the card using the UFS protocol.

Abstract translation: 公开了可移动存储卡鉴别系统和方法。 特别地，示例性实施例区分安全数字（SD）卡和符合SD外形尺寸但支持通用闪存存储（UFS）协议的其他可移动存储卡。 也就是说，主机可以具有支持SD卡形状因子的插座，并且被配置为接收设备。 在使用中，将可移动存储卡插入插座中，并且使用SD兼容询问信号，主机询问插入的卡上的公共区域。 公共区域包括与卡的能力描述符相关的信息。 SD兼容卡将响应诸如关于SD协议能力的能力描述符的信息，而符合UFS的卡将响应该卡符合UFS的指示。 然后，主机可以使用UFS协议重新启动与该卡的通信。

公开(公告)号：WO2015013460A1

公开(公告)日：2015-01-29

申请号：PCT/US2014/047908

申请日：2014-07-23

Applicant: QUALCOMM INCORPORATED

Inventor： SHACHAM, Assaf ,  LANEL, Itai ,  HAIM, Maya

IPC: G06F11/07 ,  G06F13/00

CPC classification number: G06F11/0793 ,  G06F11/0721 ,  G06F11/0745 ,  G06F11/0772 ,  G06F11/3024 ,  G06F11/3409 ,  G06F13/00 ,  G06F2201/86

Abstract: A method for error detection and recovery is provided in which a host controller and host software collaborate together. The host controller may: detect an error condition, set an error interrupt or register, and/or halt task execution or processing at the host controller. The host software may: detect an error condition as a result of the host controller having set the error interrupt or register; performs error handling, and clears the error condition. The host controller then resumes execution or processing of tasks upon detecting that error condition has been cleared by the host software.

Abstract translation: 提供了一种用于错误检测和恢复的方法，其中主机控制器和主机软件协同工作。 主机控制器可以：在主机控制器处检测错误状况，设置错误中断或寄存器，和/或停止任务执行或处理。 主机软件可以：由主机控制器设置错误中断或寄存器的结果来检测错误状况; 执行错误处理，并清除错误条件。 主机控制器在检测到主机软件已经清除了错误状况后，继续执行或处理任务。

公开(公告)号：WO2017136069A1

公开(公告)日：2017-08-10

申请号：PCT/US2016/068865

申请日：2016-12-28

Applicant: QUALCOMM INCORPORATED

Inventor： SHACHAM, Assaf ,  YIFRACH, Shaul; Yohai ,  SKULSKY, Eyal

IPC: G06F13/38 ,  G06F21/85 ,  H04L12/46

CPC classification number: G06F13/1673 ,  G06F12/1408 ,  G06F12/1466 ,  G06F13/385 ,  G06F13/4068 ,  G06F13/4282 ,  G06F21/602 ,  G06F21/85 ,  G06F2212/402 ,  H04L12/46

Abstract: Aspects disclosed in the detailed description include inline cryptographic engine (ICE) for peripheral component interconnect express (PCIe). In this regard, in one aspect, an ICE is provided in a PCIe root complex (RC) in a host system. The PCIe RC is configured to receive at least one transport layer packet (TLP), which includes a TLP prefix, from a storage device. In a non-limiting example, the TLP prefix includes transaction-specific information that may be used by the ICE to provide data encryption and decryption. By providing the ICE in the PCIe RC and receiving the transaction-specific information in the TLP prefix, it is possible to encrypt and decrypt data in the PCIe RC in compliance with established standards, thus ensuring adequate protection during data exchange between the PCIe RC and the storage device.

Abstract translation: 详细描述中公开的方面包括用于外围组件互连表达（PCIe）的内联密码引擎（ICE）。 就此而言，在一个方面中，ICE在主机系统中的PCIe根联合体（RC）中提供。 PCIe RC被配置为从存储设备接收至少一个包括TLP前缀的传输层分组（TLP）。 在非限制性示例中，TLP前缀包括可由ICE用来提供数据加密和解密的交易专用信息。 通过在PCIe RC中提供ICE并在TLP前缀中接收事务特定信息，可以根据既定标准对PCIe RC中的数据进行加密和解密，从而确保在PCIe RC和 存储设备。

公开(公告)号：WO2015038325A1

公开(公告)日：2015-03-19

申请号：PCT/US2014/052667

申请日：2014-08-26

Applicant: QUALCOMM INCORPORATED

Inventor： RAVIV, Dolev ,  BROKHMAN, Tatyana ,  HAIM, Maya ,  SHACHAM, Assaf

IPC: G06F13/38

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0679 ,  G06F13/385 ,  G06F2206/1014

Abstract: Ascertaining command completion in flash memories is disclosed. An exemplary aspect includes eliminating the software lock and the outstanding requests variable and replacing them with a transfer request completion register. The transfer request completion register may be mapped to the universal flash storage (UFS) Transfer Protocol (UTP) Transfer Request List (UTRL) slots. The controller of the host - a hardware component - may set the bit in the transfer request completion register on transfer request completion at the same time the doorbell register is cleared. After this bit has been read, the bit in the transfer request completion register is cleared.

Abstract translation: 公开闪存中的确定命令完成。 示例性方面包括消除软件锁定和未完成的请求变量并用传送请求完成寄存器替换它们。 转移请求完成寄存器可以映射到通用闪存存储（UFS）传输协议（UTP）传输请求列表（UTRL）槽。 主机的控制器 - 硬件组件 - 可以在传输请求完成时将该位置位，同时将门铃寄存器清零。 读取该位后，转移请求完成寄存器中的位将被清零。