公开(公告)号：WO2007127938A2

公开(公告)日：2007-11-08

申请号：PCT/US2007/067668

申请日：2007-04-27

Applicant: QUALCOMM INCORPORATED ,  SHIH, Garret Webster

Inventor： SHIH, Garret Webster

IPC: G06F17/14

CPC classification number: G06F17/142 ,  H04L27/265

Abstract: A processor for performing a fast Fourier transform or inverse fast Fourier transform comprises a radix-2 butterfly structure; and a radix-4 butterfly structure. A method of performing a fast Fourier transform or inverse fast Fourier transform comprises selectively performing a radix-2 butterfly operation on an input data stream; and selectively performing a radix-4 butterfly operation on one of a result produced by the radix-2 butterfly operation and the input data stream. Apparatus for performing a fast Fourier transform or inverse fast Fourier transform comprises means for selectively performing a radix-2 butterfly operation on an input data stream; and means for selectively performing a radix-4 butterfly operation on one of a result produced by the radix-2 butterfly operation and the input data stream. A communication device for transmitting or receiving information, including an inverse fast Fourier transform module or fast Fourier transform module, comprises a radix-2 butterfly structure having inputs and outputs; a radix-4 butterfly structure having inputs coupled to the radix-2 butterfly structure outputs; and a multiplexer alternately coupling the data stream to the inputs of the radix-2 butterfly structure or to the inputs of the radix-4 butterfly structure, whereby the module can perform two different resolution inverse fast Fourier transforms or fast Fourier transforms dependent on the inputs selected.

Abstract translation: 用于执行快速傅里叶变换或快速傅里叶逆变换的处理器包括基2 - 蝶形结构; 和四分之一蝴蝶结构。 一种执行快速傅立叶变换或快速傅立叶逆变换的方法包括：有选择地对输入数据流执行基2蝶形运算; 并且对由基数-2蝶形运算和输入数据流产生的结果之一选择性地执行基4运算。 用于执行快速傅里叶变换或快速傅里叶逆变换的装置包括用于选择性地对输入数据流执行基2蝶形运算的装置; 以及用于根据由基数2蝶形运算和输入数据流产生的结果之一选择性地执行基数-4蝶形运算的装置。 一种用于发送或接收信息的通信设备，包括快速傅里叶逆变换模块或快速傅立叶变换模块，包括具有输入和输出的基2蝶形结构; 具有耦合到基2蝶形结构输出的输入的基数-4蝶形结构; 和多路复用器将数据流交替地耦合到基2蝶形结构的输入或基数-4蝶形结构的输入，由此该模块可以执行取决于输入的两个不同分辨率的快速傅立叶逆变换或快速傅里叶变换 选择。

公开(公告)号：WO2014042819A1

公开(公告)日：2014-03-20

申请号：PCT/US2013/055335

申请日：2013-08-16

Applicant: QUALCOMM INCORPORATED

Inventor： MATHEW, Deepak ,  SHIH, Garret Webster ,  FRIDMAN, Jose ,  BROWN, Robin Lee

IPC: H04W52/02

CPC classification number: H04W52/02 ,  H04W52/0245 ,  H04W52/028 ,  H04W52/0287 ,  Y02D70/00 ,  Y02D70/1222 ,  Y02D70/1242 ,  Y02D70/1262 ,  Y02D70/142 ,  Y02D70/146

Abstract: A system and method dynamically scale power consumed by the circuitry of an electronic device based on channel state and/or data rate. The electronic device then operates according to the power scaling. The scaling may be in accordance with an effective data rate, a number of multiple input multiple output (MIMO) layers, receiver type, a cell scenario, or a number of carriers. A number of MIMO layers can be predicted based on at least one of channel conditions or a channel quality index (CQI).

Abstract translation: 系统和方法基于信道状态和/或数据速率来动态地缩放由电子设备的电路消耗的功率。 电子设备然后根据功率缩放来操作。 缩放可以根据有效数据速率，多输入多输出（MIMO）层，接收器类型，单元方案或多个载波来实现。 可以基于信道条件或信道质量指数（CQI）中的至少一个来预测多个MIMO层。

公开(公告)号：EP2013762A1

公开(公告)日：2009-01-14

申请号：EP07761537.5

申请日：2007-04-29

Applicant: QUALCOMM Incorporated

Inventor： SHIH, Garret Webster

IPC: G06F15/78

CPC classification number: G06F15/7867 ,  G06F9/3001 ,  G06F9/30181 ,  G06F9/3897

Abstract: General purpose array processing techniques including processing methods and apparatus. Processors may include parallel processing paths designed with reusable computational components such as multipliers, multiplexers, and ALUs. Flow of data through the paths and operations performed may be controlled based on opcodes. Processors may be shared, scalable, and configured to perform matrix operations. In particular, such operation may be useful for physical sections of MIMO-OFDM communication systems.

公开(公告)号：WO2014005119A1

公开(公告)日：2014-01-03

申请号：PCT/US2013/048764

申请日：2013-06-28

Applicant: QUALCOMM INCORPORATED

Inventor： GRUBER, Hans Georg ,  DRAVIDA, Subra ,  SUBRAHMANYA, Parvathanathan ,  NAWARE, Vidyut M. ,  O'SHEA, Helena Deirdre ,  SHIH, Garret Webster ,  THURSTON, Jason

IPC: H04L29/06 ,  H04L7/04 ,  H04L1/00

CPC classification number: H03M13/09 ,  H04L1/004 ,  H04L1/0061 ,  H04L1/0072

Abstract: A method, an apparatus, and a computer program product for communication within a wireless terminal. The method can be implemented using dedicated logic and managed and controlled by state machines and/or sequencers. Data received or provided in a memory of a first integrated circuit of a terminal is encoded and transmitted in a data packet to a second integrated circuit. A header identifying the data type and providing a destination is included in the data packet. The destination may be identified as a memory address memory of the second integrated circuit that is mapped to a corresponding memory address of the first integrated circuit at which the data is received. In an aspect, the apparatus receives a header, detects an error in the received header, determines a failure to identify a packet boundary when the error is detected, and performs a search operation to identify the packet boundary.

Abstract translation: 一种用于在无线终端内进行通信的方法，装置和计算机程序产品。 该方法可以使用专用逻辑实现，并由状态机和/或定序器进行管理和控制。 接收或提供在终端的第一集成电路的存储器中的数据被编码并在数据分组中被发送到第二集成电路。 识别数据类型并提供目的地的报头被包括在数据分组中。 目的地可以被识别为第二集成电路的存储器地址存储器，其被映射到接收数据的第一集成电路的相应存储器地址。 在一方面，该装置接收报头，检测出接收到的报头中的错误，确定在检测到错误时识别分组边界的故障，并执行识别分组边界的搜索操作。

公开(公告)号：WO2007127971A1

公开(公告)日：2007-11-08

申请号：PCT/US2007/067721

申请日：2007-04-29

Applicant: QUALCOMM Incorporated ,  SHIH, Garret Webster

Inventor： SHIH, Garret Webster

IPC: G06F15/78

CPC classification number: G06F15/7867 ,  G06F9/3001 ,  G06F9/30181 ,  G06F9/3897

Abstract: General purpose array processing techniques including processing methods and apparatus. Processors may include parallel processing paths designed with reusable computational components such as multipliers, multiplexers, and ALUs. Flow of data through the paths and operations performed may be controlled based on opcodes. Processors may be shared, scalable, and configured to perform matrix operations. In particular, such operation may be useful for physical sections of MIMO-OFDM communication systems.

Abstract translation: 通用阵列处理技术，包括处理方法和装置。 处理器可以包括用可重复使用的计算组件（例如乘法器，多路复用器和ALU）设计的并行处理路径。 通过路径的数据流和执行的操作可以基于操作码来控制。 处理器可以被共享，可扩展和配置为执行矩阵操作。 特别地，这种操作对于MIMO-OFDM通信系统的物理部分可能是有用的。

公开(公告)号：WO2007127941A2

公开(公告)日：2007-11-08

申请号：PCT/US2007/067673

申请日：2007-04-27

Applicant: QUALCOMM INCORPORATED ,  SHIH, Garret Webster

Inventor： SHIH, Garret Webster

IPC: H03M13/41

CPC classification number: H03M13/4107 ,  H03M13/395 ,  H03M13/3961 ,  H03M13/4176

Abstract: Viterbi decoding techniques that include multi-stage Viterbi decoding of encoded signals. Such techniques include radix-4 two stage decoding. The encoded signals may include soft decision signals. A Viterbi decoder may include a branch metric generator, a trellis interconnect, an add-compare element, a path metric memory, and a traceback element. The add-compare element may include a plurality of add- compare-select units that each select two trace bits per clock cycle. The traceback element may write, decode, and trace stored trace bits to decode the encoded signal.

Abstract translation: 维特比解码技术，包括编码信号的多级维特比解码。 这样的技术包括基数为4的两阶段解码。 编码信号可以包括软判决信号。 维特比解码器可以包括分支度量发生器，网格互连，加法比较元件，路径度量存储器和追溯元件。 加法比较元件可以包括多个加法比较选择单元，每个单位每个时钟周期选择两个跟踪位。 追溯元素可以写入，解码和跟踪存储的跟踪位以解码编码信号。

公开(公告)号：EP2896250B1

公开(公告)日：2017-10-04

申请号：EP13756761.6

申请日：2013-08-16

Applicant: Qualcomm Incorporated

Inventor： MATHEW, Deepak ,  SHIH, Garret Webster ,  FRIDMAN, Jose ,  BROWN, Robin Lee

IPC: H04W52/02

CPC classification number: H04W52/02 ,  H04W52/0245 ,  H04W52/028 ,  H04W52/0287 ,  Y02D70/00 ,  Y02D70/1222 ,  Y02D70/1242 ,  Y02D70/1262 ,  Y02D70/142 ,  Y02D70/146

Abstract: A system and method dynamically scale power consumed by the circuitry of an electronic device based on channel state and/or data rate. The electronic device then operates according to the power scaling. The scaling may be in accordance with an effective data rate, a number of multiple input multiple output (MIMO) layers, receiver type, a cell scenario, or a number of carriers. A number of MIMO layers can be predicted based on at least one of channel conditions or a channel quality index (CQI).

Abstract translation: 系统和方法基于信道状态和/或数据速率动态地缩放由电子设备的电路消耗的功率。 电子设备然后根据功率缩放进行操作。 缩放可以根据有效数据速率，多输入多输出（MIMO）层的数量，接收器类型，小区场景或多个载波来进行。 可以基于信道条件或信道质量指数（CQI）中的至少一个来预测多个MIMO层。

公开(公告)号：EP2013772A2

公开(公告)日：2009-01-14

申请号：EP07761490.7

申请日：2007-04-27

Applicant: Qualcomm Incorporated

Inventor： SHIH, Garret Webster

IPC: G06F17/14

CPC classification number: G06F17/142 ,  H04L27/265

Abstract: A processor for performing a fast Fourier transform or inverse fast Fourier transform comprises a radix-2 butterfly structure; and a radix-4 butterfly structure. A method of performing a fast Fourier transform or inverse fast Fourier transform comprises selectively performing a radix-2 butterfly operation on an input data stream; and selectively performing a radix-4 butterfly operation on one of a result produced by the radix-2 butterfly operation and the input data stream. Apparatus for performing a fast Fourier transform or inverse fast Fourier transform comprises means for selectively performing a radix-2 butterfly operation on an input data stream; and means for selectively performing a radix-4 butterfly operation on one of a result produced by the radix-2 butterfly operation and the input data stream. A communication device for transmitting or receiving information, including an inverse fast Fourier transform module or fast Fourier transform module, comprises a radix-2 butterfly structure having inputs and outputs; a radix-4 butterfly structure having inputs coupled to the radix-2 butterfly structure outputs; and a multiplexer alternately coupling the data stream to the inputs of the radix-2 butterfly structure or to the inputs of the radix-4 butterfly structure, whereby the module can perform two different resolution inverse fast Fourier transforms or fast Fourier transforms dependent on the inputs selected.

Abstract translation: 用于执行快速傅里叶变换或快速傅立叶逆变换的处理器包括基2蝶形结构; 和四分之一蝴蝶结构。 执行快速傅里叶变换或快速傅立叶逆变换的方法包括：选择性地对输入数据流执行二进制2蝶形运算; 并且对由基数2蝶形运算和输入数据流产生的结果之一选择性地执行基数-4蝶形运算。 用于执行快速傅立叶变换或快速傅里叶逆变换的装置包括用于选择性地对输入数据流执行基2蝶形运算的装置; 以及用于根据由基数2蝶形运算和输入数据流产生的结果之一选择性地执行基数-4蝶形运算的装置。 用于发送或接收信息的通信设备，包括快速傅里叶逆变换模块或快速傅里叶变换模块，包括具有输入和输出的二进制2蝶形结构; 具有耦合到基2蝶形结构输出的输入的基数-4蝶形结构; 以及多路复用器将数据流交替地耦合到基2蝶形结构的输入或基数-4蝶形结构的输入，由此该模块可以执行取决于输入的两个不同分辨率的快速傅立叶逆变换或快速傅里叶变换 选择。

公开(公告)号：EP2013762B1

公开(公告)日：2018-09-19

申请号：EP07761537.5

申请日：2007-04-29

Applicant: QUALCOMM Incorporated

Inventor： SHIH, Garret Webster

IPC: G06F15/78

CPC classification number: G06F15/7867 ,  G06F9/3001 ,  G06F9/30181 ,  G06F9/3897

Abstract: General purpose array processing techniques including processing methods and apparatus. Processors may include parallel processing paths designed with reusable computational components such as multipliers, multiplexers, and ALUs. Flow of data through the paths and operations performed may be controlled based on opcodes. Processors may be shared, scalable, and configured to perform matrix operations. In particular, such operation may be useful for physical sections of MIMO-OFDM communication systems.

公开(公告)号：EP2011239A2

公开(公告)日：2009-01-07

申请号：EP07761495.6

申请日：2007-04-27

Applicant: QUALCOMM Incorporated

Inventor： SHIH, Garret Webster

IPC: H03M13/41

CPC classification number: H03M13/4107 ,  H03M13/395 ,  H03M13/3961 ,  H03M13/4176

Abstract: Viterbi decoding techniques that include multi-stage Viterbi decoding of encoded signals. Such techniques include radix-4 two stage decoding. The encoded signals may include soft decision signals. A Viterbi decoder may include a branch metric generator, a trellis interconnect, an add-compare element, a path metric memory, and a traceback element. The add-compare element may include a plurality of add- compare-select units that each select two trace bits per clock cycle. The traceback element may write, decode, and trace stored trace bits to decode the encoded signal.