公开(公告)号：WO2017131907A2

公开(公告)日：2017-08-03

申请号：PCT/US2016/068461

申请日：2016-12-22

Applicant: QUALCOMM INCORPORATED

Inventor： PARK, Hee Jun ,  STEWART, Richard

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/28 ,  G06F1/3206 ,  G06F1/3253 ,  G06F1/3275 ,  G06F12/0802 ,  G06F13/16 ,  G06F13/4068 ,  G06F2212/1021 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

公开(公告)号：EP3384395A1

公开(公告)日：2018-10-10

申请号：EP16805588.7

申请日：2016-11-03

Applicant: Qualcomm Incorporated

Inventor： DE, Subrato ,  STEWART, Richard ,  CHUN, Dexter Tamio

IPC: G06F12/06 ,  G06F12/10 ,  G06F12/1027

CPC classification number: G11C7/1072 ,  G06F3/061 ,  G06F3/0653 ,  G06F3/0685 ,  G06F12/0607 ,  G06F12/10 ,  G06F12/1027 ,  G06F13/1657 ,  G06F2212/657 ,  Y02D10/13 ,  Y02D10/14

Abstract: Systems and methods are disclosed for providing memory channel interleaving with selective power/performance optimization. One such method comprises configuring an interleaved zone for relatively higher performance tasks, a linear address zone for relatively lower power tasks, and a mixed interleaved-linear zone for tasks with intermediate performance requirements. A boundary is defined among the different zones using a sliding threshold address. The zones may be dynamically adjusted, and/or new zones dynamically created, by changing the sliding address in real-time based on system goals and application performance preferences. A request for high performance memory is allocated to a zone with lower power that minimally supports the required performance, or may be allocated to a low power memory zone with lower than required performance if the system parameters indicate a need for aggressive power conservation. Pages may be migrated between zones in order to free a memory device for powering down.

公开(公告)号：WO2017095592A1

公开(公告)日：2017-06-08

申请号：PCT/US2016/060405

申请日：2016-11-03

Applicant: QUALCOMM INCORPORATED

Inventor： DE, Subrato ,  STEWART, Richard ,  CHUN, Dexter Tamio

IPC: G06F12/06 ,  G06F12/10 ,  G06F12/1027

CPC classification number: G11C7/1072 ,  G06F3/061 ,  G06F3/0653 ,  G06F3/0685 ,  G06F12/0607 ,  G06F12/10 ,  G06F12/1027 ,  G06F13/1657 ,  G06F2212/657 ,  Y02D10/13 ,  Y02D10/14

Abstract: Systems and methods are disclosed for providing memory channel interleaving with selective power/performance optimization. One such method comprises configuring an interleaved zone for relatively higher performance tasks, a linear address zone for relatively lower power tasks, and a mixed interleaved-linear zone for tasks with intermediate performance requirements. A boundary is defined among different zones using a sliding threshold address. The zones are dynamically adjusted, and/or new zones dynamically created, by changing the sliding address in real-time based on system goals and application performance preferences. A request for high performance memory is allocated to a zone with lower power that minimally supports the required performance, or may be allocated to a low power memory zone with lower than required performance if the system parameters indicate a need for aggressive power conservation. Pages may be migrated between zones in order to free a memory device for powering down.

Abstract translation: 公开了用于提供具有选择性功率/性能优化的存储信道交织的系统和方法。 一种这样的方法包括配置用于相对较高性能任务的交织区域，用于相对较低功率任务的线性地址区域以及用于具有中等性能要求的任务的混合交织线性区域。 使用滑动阈值地址在不同区域之间定义边界。 根据系统目标和应用程序性能偏好，通过实时更改滑动地址，动态调整区域和/或动态创建新区域。 如果系统参数表明需要进行大量节能，则将对高性能内存的请求分配给功耗较低的区域，以最小程度地支持所需的性能，或者将其分配给低功耗内存区域，并且性能低于所需性能。 页面可能会在区域之间迁移，以释放内存设备的电源。

公开(公告)号：WO2017083051A1

公开(公告)日：2017-05-18

申请号：PCT/US2016/056888

申请日：2016-10-13

Applicant: QUALCOMM INCORPORATED

Inventor： STEWART, Richard ,  CHUN, Dexter Tamio ,  ARTIERI, Alain

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/3287 ,  Y02D10/172 ,  Y02D50/20

Abstract: Components of a portable computing device produce power supply voltage requests indicating requested power levels. In response to the power supply voltage requests, power multiplexers associated with the components select and couple corresponding voltage rails associated with two or more fixed-voltage power supplies to the requesting components. Power supplies may be activated and deactivated on an as-requested basis.

Abstract translation: 便携式计算设备的组件产生指示所请求的功率水平的电源电压请求。 响应于电源电压请求，与组件相关联的功率多路复用器选择并将与两个或更多个固定电压电源相关联的对应电压轨耦合到请求组件。 电源可以根据要求启动和关闭。

公开(公告)号：WO2019005281A1

公开(公告)日：2019-01-03

申请号：PCT/US2018/029457

申请日：2018-04-25

Applicant: QUALCOMM INCORPORATED

Inventor： STEWART, Richard ,  CHUN, Dexter

IPC: G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/3225 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3296 ,  G06F13/1689 ,  G06F13/4068 ,  G06F2213/0064

Abstract: Systems, methods, and computer programs are disclosed for reducing dynamic random access memory (DRAM) power consumption within a selected voltage frequency/bin. One embodiment is a method comprising receiving a selected voltage/frequency bin for operating a memory bus electrically coupling a memory controller to a dynamic random access memory (DRAM). The method monitors a bandwidth of the memory bus while operating at the selected voltage/frequency bin. The method frequency switches a clock for the memory bus, based on the monitored bandwidth, between a plurality of predefined frequencies within the selected voltage/frequency bin to maintain a target bandwidth.

公开(公告)号：WO2018212832A1

公开(公告)日：2018-11-22

申请号：PCT/US2018/024386

申请日：2018-03-26

Applicant: QUALCOMM INCORPORATED

Inventor： CHUN, Dexter ,  STEWART, Richard

IPC: G06F13/16 ,  G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/3234 ,  G06F1/3253 ,  G06F1/3287 ,  G06F13/1689 ,  G11C2207/2227

Abstract: Systems and methods are disclosed for reducing double data rate (DDR) memory power consumption via device-specific customization of DDR interface parameters. One embodiment comprises a method for minimizing double data rate (DDR) power consumption. The method selects one of a plurality of operating points for a DDR interface electrically coupling a DDR memory to a memory controller residing on a system on chip (SoC). The memory controller executes a memory test via the DDR interface at the selected operating point. During the execution of the memory test at the selected operating point, the method determines an optimal value of a setting for one or more DDR interface parameters associated with the DDR interface that minimizes memory power consumption and maintains a predetermined DDR eye margin.