公开(公告)号：WO2017069907A1

公开(公告)日：2017-04-27

申请号：PCT/US2016/053082

申请日：2016-09-22

Applicant: QUALCOMM INCORPORATED

Inventor： ARTIERI, Alain ,  PALARCHARLA, Subbarao ,  MOLL, Laurent ,  SANKURATRI, Raghu ,  BHOLE, Kedar ,  CHAMARTY, Vinod

IPC: G06F12/084 ,  G06F12/0846 ,  G06F12/127 ,  G06F12/0842 ,  G06F12/0864 ,  G06F12/123

CPC classification number: G06F12/084 ,  G06F12/0842 ,  G06F12/0846 ,  G06F12/0864 ,  G06F12/0895 ,  G06F12/123 ,  G06F12/127 ,  G06F2212/1044 ,  G06F2212/1048 ,  G06F2212/601 ,  G06F2212/62

Abstract: A cache controller adaptively partitions a shared cache. The adaptive partitioning cache controller includes tag comparison and staling logic and selection logic that are responsive to client access requests and various parameters. A component cache is assigned a target occupancy which is compared to a current occupancy. A conditional identification of stale cache lines is used to manage data stored in the shared cache. When a conflict or cache miss is identified, selection logic identifies candidates for replacement preferably among cache lines identified as stale. Each cache line is assigned to a bucket with a fixed number of buckets per component cache. Allocated cache lines are assigned to a bucket as a function of the target occupancy. After a select number of buckets are filled, subsequent allocations result in oldest cache lines being marked stale. Cache lines are deemed stale when their respective component cache active indicator is de-asserted.

Abstract translation:

缓存控制器自适应地分区共享缓存。 自适应分区高速缓存控制器包括响应于客户端访问请求和各种参数的标签比较和陈述逻辑和选择逻辑。 组件高速缓存被分配一个与当前占用率进行比较的目标占用率。 使用陈旧缓存行的条件标识来管理存储在共享缓存中的数据。 当识别冲突或高速缓存未命中时，选择逻辑优选在被标识为陈旧的高速缓存行中标识替换的候选者。 每个缓存行都分配给每个组件缓存具有固定数量的存储桶的存储桶。 分配的缓存线被分配给一个桶作为目标占用的函数。 在选定数量的桶被填满之后，后续的分配导致最早的高速缓存行被标记为陈旧。 当其各自的组件高速缓存活动指示器被取消断言时，高速缓存行被视为陈旧。

公开(公告)号：WO2016182664A1

公开(公告)日：2016-11-17

申请号：PCT/US2016/027270

申请日：2016-04-13

Applicant: QUALCOMM INCORPORATED

Inventor： LI, Yanru ,  PALACHARLA, Subbarao ,  KHAN, Moinul ,  ARTIERI, Alain ,  TOUZNI, Azzedine

IPC: G06F12/08

CPC classification number: G06F12/0888 ,  G06F12/084 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/1045 ,  G06F2212/1041 ,  G06F2212/1044 ,  G06F2212/152 ,  G06F2212/608 ,  G06F2212/65 ,  Y02D10/13

Abstract: Aspects include computing devices, systems, and methods for implementing a cache maintenance or status operation for a component cache of a system cache. A computing device may generate a component cache configuration table, assign at least one component cache indicator of a component cache to a master of the component cache, and map at least one control register to the component cache indicator by a centralized control entity. The computing device may store the component cache indicator such that the component cache indicator is accessible by the master of the component cache for discovering a virtualized view of the system cache and issuing a cache maintenance or status command for the component cache bypassing the centralized control entity. The computing device may receive the cache maintenance or status command by a control register associated with a cache maintenance or status command and the component cache bypassing the centralized control entity.

Abstract translation: 方面包括用于实现系统高速缓存的组件高速缓存的高速缓存维护或状态操作的计算设备，系统和方法。 计算设备可以生成组件高速缓存配置表，将组件高速缓存的至少一个组件高速缓存指示符分配给组件高速缓存的主设备，并且通过集中控制实体将至少一个控制寄存器映射到组件高速缓存指示器。 计算设备可以存储组件高速缓存指示符，使得组件高速缓存指示符可由组件高速缓存的主机访问，用于发现系统高速缓存的虚拟化视图，并且发出用于绕过集中控制实体的组件高速缓存的高速缓存维护或状态命令 。 计算设备可以通过与高速缓存维护或状态命令相关联的控制寄存器以及绕过集中控制实体的组件高速缓存来接收高速缓存维护或状态命令。

公开(公告)号：WO2017172268A1

公开(公告)日：2017-10-05

申请号：PCT/US2017/020811

申请日：2017-03-03

Applicant: QUALCOMM INCORPORATED

Inventor： LI, Yanru ,  CHUN, Dexter Tamio ,  ARTIERI, Alain

IPC: G06F12/0862 ,  G06F1/32

Abstract: Systems, methods, and computer programs are disclosed for method for reducing memory subsystem power. In an exemplary method, a system resource manager provides memory performance requirements for a plurality of memory clients to a double data rate (DDR) subsystem. The DDR subsystem and the system resource manager reside on a system on chip (SoC) electrically coupled to a dynamic random access memory (DRAM). A cache hit rate is determined of each of the plurality of memory clients associated with a system cache residing on the DDR subsystem. The DDR subsystem controls a DDR clock frequency based on the memory performance requirements received from the system resource manager and the cache hit rates of the plurality of memory clients.

公开(公告)号：WO2017083051A1

公开(公告)日：2017-05-18

申请号：PCT/US2016/056888

申请日：2016-10-13

Applicant: QUALCOMM INCORPORATED

Inventor： STEWART, Richard ,  CHUN, Dexter Tamio ,  ARTIERI, Alain

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/3287 ,  Y02D10/172 ,  Y02D50/20

Abstract: Components of a portable computing device produce power supply voltage requests indicating requested power levels. In response to the power supply voltage requests, power multiplexers associated with the components select and couple corresponding voltage rails associated with two or more fixed-voltage power supplies to the requesting components. Power supplies may be activated and deactivated on an as-requested basis.

Abstract translation: 便携式计算设备的组件产生指示所请求的功率水平的电源电压请求。 响应于电源电压请求，与组件相关联的功率多路复用器选择并将与两个或更多个固定电压电源相关联的对应电压轨耦合到请求组件。 电源可以根据要求启动和关闭。

公开(公告)号：EP3436956A1

公开(公告)日：2019-02-06

申请号：EP17712586.1

申请日：2017-03-03

Applicant: Qualcomm Incorporated

Inventor： LI, Yanru ,  CHUN, Dexter Tamio ,  ARTIERI, Alain

IPC: G06F12/0862 ,  G06F1/32

公开(公告)号：WO2022231711A1

公开(公告)日：2022-11-03

申请号：PCT/US2022/020268

申请日：2022-03-14

Applicant: QUALCOMM INCORPORATED

Inventor： ARTIERI, Alain ,  GUPTA, Rakesh Kumar ,  PALACHARLA, Subbarao ,  BHOLE, Kedar ,  MOLL, Laurent Rene ,  SPITALE, Carlo ,  SINGHAI, Sparsh ,  THOZIYOOR, Shyamkumar ,  TUMMALA, Gopi ,  AVOINNE, Christophe ,  GINDE, Samir ,  HASSAN, Syed Minhaj ,  LECLER, Jean-Jacques ,  VINCI, Luigi

IPC: G06F12/121

Abstract: Data caching may include storing data associated with DRAM transaction requests in data storage structures organized in a manner corresponding to the DRAM bank, bank group and rank organization. Data may be selected for transfer to the DRAM by selecting among the data storage structures.

公开(公告)号：WO2018182853A1

公开(公告)日：2018-10-04

申请号：PCT/US2018/017274

申请日：2018-02-07

Applicant: QUALCOMM INCORPORATED

Inventor： ARTIERI, Alain ,  TRAN, Jean-Marie

IPC: G06F1/32 ,  G06F1/18

CPC classification number: G06F1/3296 ,  G06F1/189 ,  G06F1/324 ,  H03K5/1565 ,  Y02D10/126 ,  Y02D10/172

Abstract: An integrated circuit (IC) is disclosed herein for power management using duty cycles. In an example aspect, the integrated circuit includes multiple power domains, each of which includes a respective power state controller. The power state controller acts as a bridge between global supply lines of the integrated circuit and local supply lines of the respective power domain. Global supply lines can include a first global power rail, a second global power rail, and a global clock tree. Local supply lines can include a local power rail and a local clock tree. In operation, a power state controller adjusts a power state of the respective power domain in accordance with a duty cycle. A timeslot corresponding to the duty cycle can be separated into multiple time periods with durations of the time periods being based on the duty cycle.

公开(公告)号：WO2016010706A1

公开(公告)日：2016-01-21

申请号：PCT/US2015/037681

申请日：2015-06-25

Applicant: QUALCOMM INCORPORATED

Inventor： PALACHARLA, Subbarao ,  KHAN, Moinul ,  ARTIERI, Alain ,  BHOLE, Kedar ,  CHAMARTY, Vinod ,  CHAURASIA, Pankaj ,  SANKURATRI, Raghu

IPC: G06F12/08

CPC classification number: G06F12/0893 ,  G06F12/084 ,  G06F12/0895 ,  G06F12/10 ,  G06F12/12 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/152 ,  G06F2212/601 ,  G06F2212/6046 ,  Y02D10/13

Abstract: Aspects include computing devices, systems, and methods for partitioning a system cache by sets and ways into component caches. A system cache memory controller may manage the component caches and manage access to the component caches. The system cache memory controller may receive system cache access requests specifying component cache identifiers, and match the component cache identifiers with records correlating traits of the component cache identifiers with in a component cache configuration table. The component cache traits may include a set shift trait, set offset trait, and target ways, which may define the locations of the component caches in the system cache. The system cache memory controller may also receive a physical address for the system cache in the system cache access request, determine an indexing mode for the component cache, and translate the physical address for the component cache.

Abstract translation: 方面包括计算设备，系统和用于通过集合和方式将系统高速缓存分组到组件高速缓存中的方法。 系统高速缓冲存储器控制器可以管理组件高速缓存并管理对组件高速缓存的访问。 系统高速缓冲存储器控制器可以接收指定组件高速缓存标识符的系统高速缓存访​​问请求，并且将组件高速缓存标识符与组件高速缓存标识符的特征与组件高速缓存配置表相关联的记录进行匹 组件缓存特征可以包括设置的移动特征，设置偏移特征和目标方式，其可以定义系统高速缓存中的组件高速缓存的位置。 系统高速缓冲存储器控制器还可以在系统高速缓存访​​问请求中接收系统高速缓存的物理地址，确定组件高速缓存的索引模式，并转换组件高速缓存的物理地址。

公开(公告)号：EP3170085A1

公开(公告)日：2017-05-24

申请号：EP15734019.1

申请日：2015-06-25

Applicant: Qualcomm Incorporated

Inventor： PALACHARLA, Subbarao ,  KHAN, Moinul ,  ARTIERI, Alain ,  BHOLE, Kedar ,  CHAMARTY, Vinod ,  CHAURASIA, Pankaj ,  SANKURATRI, Raghu

IPC: G06F12/08

CPC classification number: G06F12/0893 ,  G06F12/084 ,  G06F12/0895 ,  G06F12/10 ,  G06F12/12 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/152 ,  G06F2212/601 ,  G06F2212/6046 ,  Y02D10/13

Abstract: Aspects include computing devices, systems, and methods for partitioning a system cache by sets and ways into component caches. A system cache memory controller may manage the component caches and manage access to the component caches. The system cache memory controller may receive system cache access requests specifying component cache identifiers, and match the component cache identifiers with records correlating traits of the component cache identifiers with in a component cache configuration table. The component cache traits may include a set shift trait, set offset trait, and target ways, which may define the locations of the component caches in the system cache. The system cache memory controller may also receive a physical address for the system cache in the system cache access request, determine an indexing mode for the component cache, and translate the physical address for the component cache.

Abstract translation: 方面包括计算设备，系统，和用于分割由多组和方式的系统的高速缓存成组分缓存的方法。 一种系统，高速缓冲存储器控制器可以管理组件的高速缓存和管理对组件的高速缓存。 系统高速缓存存储器控制器可以接收指定部件缓存标识系统缓存的访问请求，并与记录在组件缓存配置表进行相关组件缓存标识的性状与匹配部件缓存标识。 组件的高速缓存的性状可以包括一组移性状，设定偏移性状，和目标的方式，这可以在系统缓存定义组件的高速缓存的位置。 因此，该系统的高速缓冲存储器控制器可接收的物理地址为系统中的高速缓存访​​问请求的高速缓存系统，确定性矿索引模式为组件高速缓存，和用于该组件的高速缓存翻译的物理地址。

公开(公告)号：EP3436959A1

公开(公告)日：2019-02-06

申请号：EP17711940.1

申请日：2017-03-03

Applicant: QUALCOMM Incorporated

Inventor： LI, Yanru ,  CHUN, Dexter Tamio ,  ARTIERI, Alain

IPC: G06F13/16 ,  G06F1/32