公开(公告)号：WO2016036572A2

公开(公告)日：2016-03-10

申请号：PCT/US2015/047153

申请日：2015-08-27

Applicant: QUALCOMM INCORPORATED

Inventor： AMARILIO, Lior ,  GOLUBITSKI, Alexander ,  HALLER, Haim, Hagay ,  KOLMAKOV, Felix ,  STHOEGER, Gilad

IPC: H03K5/13

CPC classification number: H03K5/133 ,  G06F1/10 ,  G06F13/4068 ,  G06F13/4221 ,  G11C19/00 ,  H03K5/13 ,  H03K2005/0015 ,  Y02D10/14 ,  Y02D10/151

Abstract: Delay circuits, and related systems and methods are disclosed. In one aspect, a delay circuit is provided that uses logic to delay accurately an output enable signal to reduce or avoid data hazards within a slave device. The delay circuit includes two shift register chains configured to receive an output enable in signal based on a slow clock. A first shift register chain is clocked by a positive edge of a fast clock, and provides a first strobe signal. A second shift register chain is clocked by a negative edge of the fast clock, and provides a second strobe signal. The logic uses the first and second strobe signals, and the output enable in signal, to provide a delayed output enable out signal. The delay circuit provides a highly accurate time delay for the output enable signal to reduce or avoid data hazards in an area and power efficient manner.

Abstract translation: 公开了延迟电路以及相关的系统和方法。 在一个方面，提供了一种延迟电路，其使用逻辑来准确地延迟输出使能信号以减少或避免从属装置内的数据危险。 延迟电路包括两个移位寄存器链，其被配置为基于慢时钟来接收输出使能信号。 第一移位寄存器链由快时钟的上升沿计时，并提供第一选通信号。 第二个移位寄存器链由快速时钟的下降沿提供时钟，并提供第二个选通信号。 该逻辑使用第一和第二选通信号以及输出使能信号来提供延迟的输出使能输出信号。 延迟电路为输出使能信号提供高度精确的时间延迟，从而减少或避免区域中的数据危险和节能方式。

公开(公告)号：EP3189591A2

公开(公告)日：2017-07-12

申请号：EP15762863.7

申请日：2015-08-27

Applicant: QUALCOMM Incorporated

Inventor： AMARILIO, Lior ,  GOLUBITSKI, Alexander ,  HALLER, Haim, Hagay ,  KOLMAKOV, Felix ,  STHOEGER, Gilad

IPC: H03K5/13 ,  G06F1/12

CPC classification number: H03K5/133 ,  G06F1/10 ,  G06F13/4068 ,  G06F13/4221 ,  G11C19/00 ,  H03K5/13 ,  H03K2005/0015 ,  Y02D10/14 ,  Y02D10/151

Abstract: Delay circuits, and related systems and methods are disclosed. In one aspect, a delay circuit is provided that uses logic to delay accurately an output enable signal to reduce or avoid data hazards within a slave device. The delay circuit includes two shift register chains configured to receive an output enable in signal based on a slow clock. A first shift register chain is clocked by a positive edge of a fast clock, and provides a first strobe signal. A second shift register chain is clocked by a negative edge of the fast clock, and provides a second strobe signal. The logic uses the first and second strobe signals, and the output enable in signal, to provide a delayed output enable out signal. The delay circuit provides a highly accurate time delay for the output enable signal to reduce or avoid data hazards in an area and power efficient manner.

Abstract translation: 延迟电路以及相关的系统和方法被公开。 在一个方面，提供了一种延迟电路，其使用逻辑来准确地延迟输出使能信号以减少或避免从属装置内的数据危险。 延迟电路包括两个移位寄存器链，其被配置为基于慢时钟来接收输出使能信号。 第一移位寄存器链由快时钟的上升沿计时，并提供第一选通信号。 第二个移位寄存器链由快速时钟的下降沿提供时钟，并提供第二个选通信号。 该逻辑使用第一和第二选通信号以及输出使能信号来提供延迟的输出使能输出信号。 延迟电路为输出使能信号提供高度精确的时间延迟，以减少或避免区域中的数据危险和功率高效的方式。

公开(公告)号：WO2015138244A1

公开(公告)日：2015-09-17

申请号：PCT/US2015/019194

申请日：2015-03-06

Applicant: QUALCOMM INCORPORATED

Inventor： ZILBERSHTEIN, Michael ,  STHOEGER, Gilad ,  KHAZIN, Alexander

IPC: G06F11/22

CPC classification number: G06F11/349 ,  G06F11/221 ,  G06F11/3027

Abstract: Systems and methods to detect errors and record actions on a bus are disclosed. In one embodiment, the bus is a serial low-power interchip media bus (SLIMbus) within a computing device. The SLIMbus is coupled to peripherals and a sniffer is positioned within the computing device and coupled to the SLIMbus. The sniffer mimics another SLIMbus peripheral. However, the sniffer uses a pair of multiplexers to know when to record data on the SLIMbus. The data, including the control header and payload of the data signal is captured and logged. The logged data is then exported to memory where it can be further processed so as to help debug communication on the SLIMbus.

Abstract translation: 公开了在总线上检测错误和记录动作的系统和方法。 在一个实施例中，总线是计算设备内的串行低功率芯片间介质总线（SLIMbus）。 SLIMbus耦合到外围设备，嗅探器位于计算设备内并与SLIMbus相连。 嗅探器模仿另一个SLIMbus外设。 然而，嗅探器使用一对多路复用器来知道何时在SLIMbus上记录数据。 捕获并记录数据，包括数据信号的控制头和有效载荷。 然后将记录的数据导出到存储器，以便进一步处理它们，以帮助调试SLIMbus上的通信。

公开(公告)号：WO2015073379A1

公开(公告)日：2015-05-21

申请号：PCT/US2014/064864

申请日：2014-11-10

Applicant: QUALCOMM INCORPORATED

Inventor： STHOEGER, Gilad ,  ZILBERSTEIN, Michael ,  KHAZIN, Alexander ,  LEVIN, Ben

IPC: G06F13/42

CPC classification number: G06F13/4282 ,  G06F1/12 ,  G06F13/423 ,  G06F13/4291 ,  Y02D10/14 ,  Y02D10/151

Abstract: A serial low-power inter-chip media bus communications link is deployed in apparatus having multiple Integrated Circuit devices. Communications capabilities of a device coupled to the communications link may be determined and configuration or framing message may be sent to the first device based on the capabilities. The messages may be transmitted on a primary data line of the communications link with a clock used to control timing of transmission on at least the primary data line. The communications capabilities can include information identifying a number of data wires supported by or coupled to the device. A first device may be configured to communicate with a second device over a secondary data line, which may be reserved for such direct communication. Communications on the secondary data line may be synchronized using the clock signal and may be controlled by a different protocol than the protocol used for the primary data line.

Abstract translation: 串行低功率芯片间媒体总线通信链路部署在具有多个集成电路设备的设备中。 可以确定耦合到通信链路的设备的通信能力，并且可以基于能力将配置或成帧消息发送到第一设备。 消息可以在具有用于控制至少主数据线上的传输定时的时钟的通信链路的主数据线上发送。 通信能力可以包括识别由设备支持或耦合到设备的多个数据线的信息。 第一设备可以被配置为通过辅助数据线与第二设备进行通信，次级数据线可以被保留用于这种直接通信。 次数据线上的通信可以使用时钟信号同步，并且可以由与用于主数据线的协议不同的协议来控制。

公开(公告)号：EP3069260A1

公开(公告)日：2016-09-21

申请号：EP14803307.9

申请日：2014-11-10

Applicant: QUALCOMM INCORPORATED

Inventor： STHOEGER, Gilad ,  ZILBERSTEIN, Michael ,  KHAZIN, Alexander ,  LEVIN, Ben

IPC: G06F13/42

CPC classification number: G06F13/4282 ,  G06F1/12 ,  G06F13/423 ,  G06F13/4291 ,  Y02D10/14 ,  Y02D10/151

Abstract: A serial low-power inter-chip media bus communications link is deployed in apparatus having multiple Integrated Circuit devices. Communications capabilities of a device coupled to the communications link may be determined and configuration or framing message may be sent to the first device based on the capabilities. The messages may be transmitted on a primary data line of the communications link with a clock used to control timing of transmission on at least the primary data line. The communications capabilities can include information identifying a number of data wires supported by or coupled to the device. A first device may be configured to communicate with a second device over a secondary data line, which may be reserved for such direct communication. Communications on the secondary data line may be synchronized using the clock signal and may be controlled by a different protocol than the protocol used for the primary data line.