INTEGRATED CIRCUITS WITH CACHE-COHERENCY
    3.
    发明公开
    INTEGRATED CIRCUITS WITH CACHE-COHERENCY 审中-公开
    与高速缓存一致性集成电路的

    公开(公告)号:EP2771793A4

    公开(公告)日:2015-07-15

    申请号:EP12844279

    申请日:2012-10-25

    Abstract: An improved cache coherency controller, method of operation, and system of such is provided. Traffic from coherent agents to shared targets can flow on different channels through the coherency controller. This improves quality of service for performance sensitive agents. Furthermore, data transfer is performed on a separate network from coherency control. This minimizes the distance of data movement, reducing congestion for the physical routing of wires on the chip and reduces the power consumption for data transfers.

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