公开(公告)号：IN3083CHN2014A

公开(公告)日：2015-07-03

申请号：IN3083CHN2014

申请日：2014-04-24

Applicant: QUALCOMM TECHNOLOGIES INC

Inventor： MOLL LAURENT RENE ,  LECLER JEAN JACQUES

IPC: G06F12/00 ,  G06F12/08

Abstract: An improved cache coherency controller method of operation and system of such is provided. Traffic from coherent agents to shared targets can flow on different channels through the coherency controller. This improves quality of service for performance sensitive agents. Furthermore data transfer is performed on a separate network from coherency control. This minimizes the distance of data movement reducing congestion for the physical routing of wires on the chip and reduces the power consumption for data transfers.

公开(公告)号：EP2771793A4

公开(公告)日：2015-07-15

申请号：EP12844279

申请日：2012-10-25

Applicant: QUALCOMM TECHNOLOGIES INC

Inventor： MOLL LAURENT RENE ,  LECLER JEAN-JACQUES

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/0815 ,  G06F2212/1016 ,  G06F2212/621 ,  Y02B60/1225 ,  Y02D10/13

Abstract: An improved cache coherency controller, method of operation, and system of such is provided. Traffic from coherent agents to shared targets can flow on different channels through the coherency controller. This improves quality of service for performance sensitive agents. Furthermore, data transfer is performed on a separate network from coherency control. This minimizes the distance of data movement, reducing congestion for the physical routing of wires on the chip and reduces the power consumption for data transfers.