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    Mosaic focal plane array
    1.
    发明授权
    Mosaic focal plane array 有权

    公开(公告)号：US12261186B2

    公开(公告)日：2025-03-25

    申请号：US17212085

    申请日：2021-03-25

    Applicant: Raytheon Company

    Inventor： David J. Gulbransen ,  Sean P. Kilcoyne ,  Eric Miller ,  Matthew D. Chambers ,  Eric J. Beuville ,  Andrew E. Gin ,  Adam M. Kennedy

    IPC: H01L25/00 ,  H01L21/66 ,  H01L23/00 ,  H01L27/146

    Abstract: A focal plane array includes a mosaic integrated circuit device having a plurality of discrete integrated circuit tiles mounted on a motherboard. The focal plane array includes an optically continuous detector array electrically connected to the mosaic integrated circuit device with an interposer disposed therebetween. The interposer is configured to adjust a pitch of the continuous detector array to match a pitch of each of the plurality of discrete integrated circuit tiles so that the optical gaps between each of the plurality of integrated circuit tiles on the motherboard are minimized and the detector array is optically continuous, having high yield over the large format focal plane array.

    Per-pixel dark reference bolometer
    2.
    发明授权
    Per-pixel dark reference bolometer 有权

    公开(公告)号：US10451487B1

    公开(公告)日：2019-10-22

    申请号：US16110367

    申请日：2018-08-23

    Applicant: RAYTHEON COMPANY

    Inventor： Adam M. Kennedy ,  Eli E. Gordon ,  Eric J. Beuville ,  Ryan Paul Boesch ,  Jeffrey K. Hamers

    IPC: G01J5/20 ,  G01J5/06 ,  G01J5/52 ,  G01J5/00

    Abstract: Microbolometer arrays incorporating per-pixel dark reference structures for non-uniformity correction. In one example a thermal imager includes a device substrate, a microbolometer array disposed on the device substrate and including a plurality of detector elements arranged in a two-dimensional array, each detector element including an imaging microbolometer and a reference microbolometer, the imaging microbolometer being configured to receive electromagnetic radiation from a viewed scene and to produce an image signal in response to receiving the electromagnetic radiation, the image signal including a component produced due to thermal noise in the respective detector element, and the reference microbolometer being shielded from receiving the electromagnetic radiation and configured to produce a reference signal indicative of the thermal noise, wherein the thermal imaging device is configured to produce an image of the viewed scene based on a combination of the image signals and the reference signals from the plurality of detector elements.

    Use of an external getter to reduce package pressure
    6.
    发明授权
    Use of an external getter to reduce package pressure 有权
    使用外部吸气剂降低包装压力

    公开(公告)号：US09570321B1

    公开(公告)日：2017-02-14

    申请号：US14887544

    申请日：2015-10-20

    Applicant: RAYTHEON COMPANY

    Inventor： Stephen H. Black ,  Adam M. Kennedy

    IPC: H01L21/322 ,  H01L23/26 ,  H01L23/544

    CPC classification number: H01L23/26 ,  H01L21/3221 ,  H01L21/3225 ,  H01L21/4817 ,  H01L21/54 ,  H01L23/041 ,  H01L23/10

    Abstract: A system and method for forming a wafer level package. In one example, a substrate used in the wafer level package includes a surface defined by a wafer level package (WLP) region and an external region, and a layer of getter material is disposed on at least a portion of the external region. According to one embodiment, the external region comprises a saw-to-reveal (STR) region of the wafer.

    Abstract translation: 一种用于形成晶片级封装的系统和方法。 在一个示例中，用于晶片级封装的衬底包括由晶片级封装（WLP）区域和外部区域限定的表面，并且吸收材料层设置在外部区域的至少一部分上。 根据一个实施例，外部区域包括晶片的锯切（STR）区域。

    METHOD OF FORMING DEPOSITED PATTERNS ON A SURFACE
    8.
    发明申请
    METHOD OF FORMING DEPOSITED PATTERNS ON A SURFACE 有权
    在表面形成沉积图案的方法

    公开(公告)号：US20150162479A1

    公开(公告)日：2015-06-11

    申请号：US14100048

    申请日：2013-12-09

    Applicant: Raytheon Company

    Inventor： Roland Gooch ,  Thomas Allan Kocian ,  Buu Diep ,  Adam M. Kennedy ,  Stephen H. Black

    IPC: H01L31/18 ,  H01L31/0232

    CPC classification number: H01L31/18 ,  B81C1/00373 ,  B81C2201/0188 ,  H01L31/02327

    Abstract: A method for forming a coating of material on selected portions of a surface of a substrate having a plurality of cavities, each cavity having outer, peripheral sidewalls extending outwardly from the surface. The method includes: providing a structure having a release agent thereon; contacting top surface of the wafer with the release agent to transfer portions of the release agent to the top surface of the wafer while bottom portions of the cavities remain spaced from the release agent to produce an intermediate structure; the release agent disposed on the top surface of the wafer and with the bottom portions of the cavities void of the release agent; exposing the intermediate structure to the material to blanket coat the material on both the release agent and the bottom portions of the cavities; and selectively removing the release agent together with the coating material while leaving the coating material on the bottom portions of the cavities.

    Abstract translation: 一种用于在具有多个空腔的基板的表面的选定部分上形成材料涂层的方法，每个空腔具有从表面向外延伸的外部周边侧壁。 该方法包括：提供其上具有脱模剂的结构; 使所述晶片的顶表面与所述脱模剂接触以将所述脱模剂的部分转移到所述晶片的顶表面，同时所述空腔的底部保持与所述脱模剂间隔开以产生中间结构; 所述脱模剂设置在所述晶片的顶表面上，并且所述空腔的底部部分脱离所述脱模剂; 将所述中间结构暴露于所述材料以在所述空腔的所述脱模剂和所述底部两者上均匀地涂覆所述材料; 并且与涂料一起选择性地除去脱模剂，同时将涂料留在空腔的底部。

    DIGITAL PIXEL HAVING HIGH SENSITIVITY AND DYNAMIC RANGE
    9.
    发明申请
    DIGITAL PIXEL HAVING HIGH SENSITIVITY AND DYNAMIC RANGE 有权

    公开(公告)号：US20210377470A1

    公开(公告)日：2021-12-02

    申请号：US16890483

    申请日：2020-06-02

    Applicant: Raytheon Company

    Inventor： Neil R. Malone ,  Micky Harris ,  Adam M. Kennedy ,  George Paloczi ,  John L. Vampola ,  Christian M. Boemler

    IPC: H04N5/355 ,  H04N5/378 ,  H04N5/3745

    Abstract: A digital pixel includes a capacitive transimpedence amplifier (CTIA) coupled to a photodiode that receives an electrical charge and output an integration voltage. An integration capacitor coupled to the CTIA accumulates the integration voltage over an integration period. A comparator compares the accumulated integration voltage with a threshold voltage and generates a control signal at a first level each time the accumulated integration voltage is greater than the threshold voltage. A charge subtraction circuit receives the control signal at the first level and discharges the accumulated integration voltage each time the control signal at the first level is received from the comparator. An analog or digital counter receives the control signal at the first level and adjusts a counter value each time the control signal is received from the comparator. An output interface communicates the counter value to an image processing circuit at an end of the integration period.

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