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1.发明申请WAFER LEVEL PACKAGE SOLDER BARRIER USED AS VACUUM GETTER 有权WAVER LEVEL PACKAGE SOLDER BARRIER用作真空灭火器公开(公告)号：US20170011977A1
公开(公告)日：2017-01-12
申请号：US15270145
申请日：2016-09-20
Applicant: RAYTHEON COMPANY
Inventor： Roland W. Gooch , Buu Q. Diep , Adam M. Kennedy , Stephen H. Black , Thomas A. Kocian
IPC: H01L23/10 , H01L27/146 , H01L23/26 , B81B7/00 , B81C1/00
CPC classification number: H01L23/10 , B81B7/0038 , B81B2201/0207 , B81C1/00269 , B81C2203/035 , H01L21/52 , H01L21/76841 , H01L23/26 , H01L23/49866 , H01L27/14618 , H01L27/14634 , H01L27/14636 , H01L27/14683 , H01L27/1469 , H01L2224/16 , H01L2924/0002 , H01L2924/00
Abstract: An electronic device and methods of manufacture thereof. One or more methods may include providing a lid wafer having a cavity and a surface surrounding the cavity and a device wafer having a detector device and a reference device. In certain examples, a solder barrier layer of titanium material may be deposited onto the surface of the lid wafer. The solder barrier layer of titanium material may further be activated to function as a getter. In various examples, the lid wafer and the device wafer may be bonded together using solder, and the solder barrier layer of titanium material may prevent the solder from contacting the surface of the lid wafer.
Abstract translation: 电子装置及其制造方法。 一种或多种方法可以包括提供具有空腔和围绕空腔的表面的盖晶片和具有检测器装置和参考装置的装置晶片。 在某些实例中，可以将钛材料的阻焊层沉积到盖晶片的表面上。 可以进一步激活钛材料的阻焊层作为吸气剂。 在各种示例中，盖晶片和器件晶片可以使用焊料接合在一起，并且钛材料的阻焊层可以防止焊料接触盖晶片的表面。
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公开(公告)号：US09520332B2
公开(公告)日：2016-12-13
申请号：US14736042
申请日：2015-06-10
Applicant: RAYTHEON COMPANY
Inventor： Roland W. Gooch , Buu Q. Diep , Adam M. Kennedy , Stephen H. Black , Thomas A. Kocian
IPC: H01L23/48 , H01L23/20 , H01L21/00 , H01L21/30 , H01L23/10 , H01L23/498 , H01L21/768 , B81B7/00 , H01L23/26 , B81C1/00 , H01L21/52 , H01L27/146
CPC classification number: H01L23/10 , B81B7/0038 , B81B2201/0207 , B81C1/00269 , B81C2203/035 , H01L21/52 , H01L21/76841 , H01L23/26 , H01L23/49866 , H01L27/14618 , H01L27/14634 , H01L27/14636 , H01L27/14683 , H01L27/1469 , H01L2224/16 , H01L2924/0002 , H01L2924/00
Abstract: An electronic device and methods of manufacture thereof. One or more methods may include providing a lid wafer having a cavity and a surface surrounding the cavity and a device wafer having a detector device and a reference device. In certain examples, a solder barrier layer of titanium material may be deposited onto the surface of the lid wafer. The solder barrier layer of titanium material may further be activated to function as a getter. In various examples, the lid wafer and the device wafer may be bonded together using solder, and the solder barrier layer of titanium material may prevent the solder from contacting the surface of the lid wafer.
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3.发明申请METHOD OF STRESS RELIEF IN ANTI-REFLECTIVE COATED CAP WAFERS FOR WAFER LEVEL PACKAGED INFRARED FOCAL PLANE ARRAYS 审中-公开用于水平包装的红外焦平面阵列的抗反射涂层盖子中的应力消除方法公开(公告)号：US20160340179A1
公开(公告)日：2016-11-24
申请号：US15227181
申请日：2016-08-03
Applicant: RAYTHEON COMPANY
Inventor： Roland W. Gooch , Buu Q. Diep , Stephen H. Black , Thomas A. Kocian , Adam M. Kennedy
CPC classification number: B81C1/00325 , B05D5/061 , B81B7/0067 , B81B2201/0207 , B81C2203/0118
Abstract: Methods for reducing wafer bow induced by an anti-reflective coating of a cap wafer are provided. The method may utilize a shadow mask having at least one opening therein that is positioned opposite recessed regions in a cap wafer. The method may further include depositing at least one layer of an anti-reflective coating material through the shadow mask onto a planar side of a cap wafer to provide a discontinuous coating on the planar side.
Abstract translation: 提供了通过盖晶片的抗反射涂层引起的减少晶片弓的方法。 该方法可以利用其中具有至少一个开口的荫罩，其位于帽晶片中的相对凹陷区域。 该方法还可以包括将至少一层抗反射涂层材料通过荫罩沉积到盖晶片的平面侧上，以在平面侧上提供不连续的涂层。
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公开(公告)号：US20150279755A1
公开(公告)日：2015-10-01
申请号：US14736042
申请日：2015-06-10
Applicant: RAYTHEON COMPANY
Inventor： Roland W. Gooch , Buu Q. Diep , Adam M. Kennedy , Stephen H. Black , Thomas A. Kocian
CPC classification number: H01L23/10 , B81B7/0038 , B81B2201/0207 , B81C1/00269 , B81C2203/035 , H01L21/52 , H01L21/76841 , H01L23/26 , H01L23/49866 , H01L27/14618 , H01L27/14634 , H01L27/14636 , H01L27/14683 , H01L27/1469 , H01L2224/16 , H01L2924/0002 , H01L2924/00
Abstract: An electronic device and methods of manufacture thereof. One or more methods may include providing a lid wafer having a cavity and a surface surrounding the cavity and a device wafer having a detector device and a reference device. In certain examples, a solder barrier layer of titanium material may be deposited onto the surface of the lid wafer. The solder barrier layer of titanium material may further be activated to function as a getter. In various examples, the lid wafer and the device wafer may be bonded together using solder, and the solder barrier layer of titanium material may prevent the solder from contacting the surface of the lid wafer.
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公开(公告)号：US09093444B2
公开(公告)日：2015-07-28
申请号：US13939400
申请日：2013-07-11
Applicant: Raytheon Company
Inventor： Roland W. Gooch , Buu Q. Diep , Adam M. Kennedy , Stephen H. Black , Thomas Allan Kocian
IPC: H01L23/48 , H01L23/544 , H01L23/02 , H01L23/06 , H01L23/498 , H01L21/768 , B81B7/00 , B81C1/00 , H01L23/26 , H01L27/146
CPC classification number: H01L23/10 , B81B7/0038 , B81B2201/0207 , B81C1/00269 , B81C2203/035 , H01L21/52 , H01L21/76841 , H01L23/26 , H01L23/49866 , H01L27/14618 , H01L27/14634 , H01L27/14636 , H01L27/14683 , H01L27/1469 , H01L2224/16 , H01L2924/0002 , H01L2924/00
Abstract: An electronic device and methods of manufacture thereof. One or more methods may include providing a lid wafer having a cavity and a surface surrounding the cavity and a device wafer having a detector device and a reference device. In certain examples, a solder barrier layer of titanium material may be deposited onto the surface of the lid wafer. The solder barrier layer of titanium material may further be activated to function as a getter. In various examples, the lid wafer and the device wafer may be bonded together using solder, and the solder barrier layer of titanium material may prevent the solder from contacting the surface of the lid wafer.
Abstract translation: 电子装置及其制造方法。 一种或多种方法可以包括提供具有空腔和围绕空腔的表面的盖晶片和具有检测器装置和参考装置的装置晶片。 在某些实例中，可以将钛材料的阻焊层沉积到盖晶片的表面上。 可以进一步激活钛材料的阻焊层作为吸气剂。 在各种示例中，盖晶片和器件晶片可以使用焊料接合在一起，并且钛材料的阻焊层可以防止焊料接触盖晶片的表面。
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Patent Agency Ranking
公开(公告)号：US20150076216A1
公开(公告)日：2015-03-19
申请号：US14468660
申请日：2014-08-26
Applicant: Raytheon Company
Inventor： Buu Q. Diep , Thomas A. Kocian , Roland W. Gooch
IPC: B23K1/20
CPC classification number: B23K1/206 , B23K1/0016 , B23K1/008 , B23K1/20 , B23K1/203 , B23K3/047 , B23K3/08 , B23K2101/40 , H01L21/67092 , H01L21/67173 , H01L21/67207 , H01L24/27 , H01L24/29 , H01L24/742 , H01L24/75 , H01L24/83 , H01L24/94 , H01L2224/0401 , H01L2224/056 , H01L2224/27318 , H01L2224/27334 , H01L2224/2745 , H01L2224/2746 , H01L2224/2781 , H01L2224/27826 , H01L2224/291 , H01L2224/29144 , H01L2224/32145 , H01L2224/32225 , H01L2224/7501 , H01L2224/75102 , H01L2224/83013 , H01L2224/83201 , H01L2224/834 , H01L2224/83815 , H01L2224/94 , H01L2924/01029 , H01L2924/014 , H01L2924/14 , H01L2924/1461 , H01L2924/181 , H01L2224/83 , H01L2924/0105 , H01L2924/00
Abstract: In certain embodiments, a system includes a deposition system and a plasma/bonding system. The deposition system deposits a solder outwardly from a substrate of a number of substrates. The plasma/bonding system comprises a plasma system configured to plasma clean the substrate and a bonding system configured to bond the substrates. The plasma/bonding system at least reduces reoxidation of the solder. In certain embodiments, a method comprises depositing solder outwardly from a substrate, removing metal oxide from the substrate, and depositing a capping layer outwardly from the substrate to at least reduce reoxidation of the solder.
Abstract translation: 在某些实施例中，系统包括沉积系统和等离子/粘合系统。 沉积系统从许多基底的衬底向外沉积焊料。 等离子体/粘合系统包括构造成等离子体清洁基板的等离子体系统和被配置为结合基板的接合系统。 等离子体/粘合系统至少减少了焊料的再氧化。 在某些实施例中，一种方法包括从衬底向外沉积焊料，从衬底去除金属氧化物，以及从衬底向外沉积覆盖层以至少减少焊料的再氧化。
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公开(公告)号：US10315918B2
公开(公告)日：2019-06-11
申请号：US15227181
申请日：2016-08-03
Applicant: RAYTHEON COMPANY
Inventor： Roland W. Gooch , Buu Q. Diep , Stephen H. Black , Thomas A. Kocian , Adam M. Kennedy
Abstract: Methods for reducing wafer bow induced by an anti-reflective coating of a cap wafer are provided. The method may utilize a shadow mask having at least one opening therein that is positioned opposite recessed regions in a cap wafer. The method may further include depositing at least one layer of an anti-reflective coating material through the shadow mask onto a planar side of a cap wafer to provide a discontinuous coating on the planar side.
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公开(公告)号：US09132496B2
公开(公告)日：2015-09-15
申请号：US14468660
申请日：2014-08-26
Applicant: Raytheon Company
Inventor： Buu Q. Diep , Thomas A. Kocian , Roland W. Gooch
CPC classification number: B23K1/206 , B23K1/0016 , B23K1/008 , B23K1/20 , B23K1/203 , B23K3/047 , B23K3/08 , B23K2101/40 , H01L21/67092 , H01L21/67173 , H01L21/67207 , H01L24/27 , H01L24/29 , H01L24/742 , H01L24/75 , H01L24/83 , H01L24/94 , H01L2224/0401 , H01L2224/056 , H01L2224/27318 , H01L2224/27334 , H01L2224/2745 , H01L2224/2746 , H01L2224/2781 , H01L2224/27826 , H01L2224/291 , H01L2224/29144 , H01L2224/32145 , H01L2224/32225 , H01L2224/7501 , H01L2224/75102 , H01L2224/83013 , H01L2224/83201 , H01L2224/834 , H01L2224/83815 , H01L2224/94 , H01L2924/01029 , H01L2924/014 , H01L2924/14 , H01L2924/1461 , H01L2924/181 , H01L2224/83 , H01L2924/0105 , H01L2924/00
Abstract: In certain embodiments, a system includes a deposition system and a plasma/bonding system. The deposition system deposits a solder outwardly from a substrate of a number of substrates. The plasma/bonding system comprises a plasma system configured to plasma clean the substrate and a bonding system configured to bond the substrates. The plasma/bonding system at least reduces reoxidation of the solder. In certain embodiments, a method comprises depositing solder outwardly from a substrate, removing metal oxide from the substrate, and depositing a capping layer outwardly from the substrate to at least reduce reoxidation of the solder.
Abstract translation: 在某些实施例中，系统包括沉积系统和等离子/粘合系统。 沉积系统从许多基底的衬底向外沉积焊料。 等离子体/粘合系统包括构造成等离子体清洁基板的等离子体系统和被配置为结合基板的接合系统。 等离子体/粘合系统至少减少了焊料的再氧化。 在某些实施例中，一种方法包括从衬底向外沉积焊料，从衬底去除金属氧化物，以及从衬底向外沉积覆盖层以至少减少焊料的再氧化。
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9.发明申请METHOD OF STRESS RELIEF IN ANTI-REFLECTIVE COATED CAP WAFERS FOR WAFER LEVEL PACKAGED INFRARED FOCAL PLANE ARRAYS 有权用于水平包装的红外焦平面阵列的抗反射涂层盖子中的应力消除方法公开(公告)号：US20140053966A1
公开(公告)日：2014-02-27
申请号：US13688714
申请日：2012-11-29
Applicant: RAYTHEON COMPANY
Inventor： Roland W. Gooch , Buu Q. Diep , Stephen H. Black , Thomas A. Kocian , Adam M. Kennedy
IPC: B05D5/06
CPC classification number: B81C1/00325 , B05D5/061 , B81B7/0067 , B81B2201/0207 , B81C2203/0118
Abstract: Methods for reducing wafer bow induced by an anti-reflective coating of a cap wafer are provided. The method may utilize a shadow mask having at least one opening therein that is positioned opposite recessed regions in a cap wafer. The method may further include depositing at least one layer of an anti-reflective coating material through the shadow mask onto a planar side of a cap wafer to provide a discontinuous coating on the planar side.
Abstract translation: 提供了通过盖晶片的抗反射涂层引起的减少晶片弓的方法。 该方法可以利用其中具有至少一个开口的荫罩，其位于帽晶片中的相对凹陷区域。 该方法还可以包括将至少一层抗反射涂层材料通过荫罩沉积到盖晶片的平面侧上，以在平面侧上提供不连续的涂层。
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10.发明授权Method of stress relief in anti-reflective coated cap wafers for wafer level packaged infrared focal plane arrays 有权用于晶圆级封装的红外焦平面阵列的抗反射涂层盖晶片中的应力消除方法公开(公告)号：US09427776B2
公开(公告)日：2016-08-30
申请号：US13688714
申请日：2012-11-29
Applicant: Raytheon Company
Inventor： Roland W. Gooch , Buu Q. Diep , Stephen H. Black , Thomas A. Kocian , Adam M. Kennedy
CPC classification number: B81C1/00325 , B05D5/061 , B81B7/0067 , B81B2201/0207 , B81C2203/0118
Abstract: Methods for reducing wafer bow induced by an anti-reflective coating of a cap wafer are provided. The method may utilize a shadow mask having at least one opening therein that is positioned opposite recessed regions in a cap wafer. The method may further include depositing at least one layer of an anti-reflective coating material through the shadow mask onto a planar side of a cap wafer to provide a discontinuous coating on the planar side.
Abstract translation: 提供了通过盖晶片的抗反射涂层引起的减少晶片弓的方法。 该方法可以利用其中具有至少一个开口的荫罩，其位于帽晶片中的相对凹陷区域。 该方法还可以包括将至少一层抗反射涂层材料通过荫罩沉积到盖晶片的平面侧上，以在平面侧上提供不连续的涂层。
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