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    LOW-STRESS DIELECTRIC LAYER, PLANARIZATION METHOD, AND LOW-TEMPERATURE PROCESSING FOR 3D-INTEGRATED ELECTRICAL DEVICE
    1.
    发明申请
    LOW-STRESS DIELECTRIC LAYER, PLANARIZATION METHOD, AND LOW-TEMPERATURE PROCESSING FOR 3D-INTEGRATED ELECTRICAL DEVICE 审中-公开

    公开(公告)号：WO2023278003A1

    公开(公告)日：2023-01-05

    申请号：PCT/US2022/026698

    申请日：2022-04-28

    Applicant: RAYTHEON COMPANY

    Inventor： FULK, Chad ,  KILCOYNE, Sean P. ,  FARRELL, Stuart ,  MILLER, Eric ,  CLARKE, Andrew

    IPC: H01L27/146 ,  H01L31/18 ,  H01L31/0224

    Abstract: An electrical device includes a substrate (12), a dielectric layer (16) supported by the substrate, and an electrically conductive vertical interconnect (18) extending through the dielectric layer. The dielectric layer may be formed at low-temperature below the thermal degradation temperature of thermally-sensitive material (14) in the device. The dielectric layer (16) may be a low-stress layer that imparts no stress or less stress than a failure stress of fragile material in the device. The dielectric layer may be formed during a processing step to planarize the electrical device at that step. The vertical interconnect (16) may be diffusion bondable with another opposing interconnect at a low-temperature below the thermal degradation temperature of thermally-sensitive material in the device. The vertical interconnect (18) may have a coefficient of thermal expansion (CTE) that is greater than a CTE of the dielectric layer (16) to facilitate 3D-integration.

    OFFSET VERTICAL INTERCONNECT AND COMPRESSION POST FOR 3D-INTEGRATED ELECTRICAL DEVICE
    2.
    发明申请
    OFFSET VERTICAL INTERCONNECT AND COMPRESSION POST FOR 3D-INTEGRATED ELECTRICAL DEVICE 审中-公开

    公开(公告)号：WO2022192107A1

    公开(公告)日：2022-09-15

    申请号：PCT/US2022/019082

    申请日：2022-03-07

    Applicant: RAYTHEON COMPANY

    Inventor： CLARKE, Andrew ,  PATTISON, James ,  FARRELL, Stuart

    IPC: H01L23/00 ,  H01L25/065 ,  H01L25/04 ,  H01L21/18

    Abstract: An electrical device including a substrate (130), a dielectric layer (120) supported by the substrate having at least one vertical post (122) disposed within a via hole (123) of the dielectric layer, and at least one electrically conductive vertical interconnect (126) laterally offset from the post. The post is configured to impart a non-tensile state to a region of the electrical device underlying the post. The coefficient of thermal expansion (CTE) of the post may be configured to cooperate with the CTE of the dielectric layer to provide the non- tensile state, such as the dielectric layer having a CTE that is equal to or greater than a CTE of the post. The dielectric layer may have a CTE that is less than the CTE of the electrically conductive vertical interconnect, and may be arranged to provide a buffer to tensile forces imparted by the vertical interconnect.

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