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    LOW-STRESS DIELECTRIC LAYER, PLANARIZATION METHOD, AND LOW-TEMPERATURE PROCESSING FOR 3D-INTEGRATED ELECTRICAL DEVICE
    1.
    发明申请
    LOW-STRESS DIELECTRIC LAYER, PLANARIZATION METHOD, AND LOW-TEMPERATURE PROCESSING FOR 3D-INTEGRATED ELECTRICAL DEVICE 审中-公开

    公开(公告)号：WO2023278003A1

    公开(公告)日：2023-01-05

    申请号：PCT/US2022/026698

    申请日：2022-04-28

    Applicant: RAYTHEON COMPANY

    Inventor： FULK, Chad ,  KILCOYNE, Sean P. ,  FARRELL, Stuart ,  MILLER, Eric ,  CLARKE, Andrew

    IPC: H01L27/146 ,  H01L31/18 ,  H01L31/0224

    Abstract: An electrical device includes a substrate (12), a dielectric layer (16) supported by the substrate, and an electrically conductive vertical interconnect (18) extending through the dielectric layer. The dielectric layer may be formed at low-temperature below the thermal degradation temperature of thermally-sensitive material (14) in the device. The dielectric layer (16) may be a low-stress layer that imparts no stress or less stress than a failure stress of fragile material in the device. The dielectric layer may be formed during a processing step to planarize the electrical device at that step. The vertical interconnect (16) may be diffusion bondable with another opposing interconnect at a low-temperature below the thermal degradation temperature of thermally-sensitive material in the device. The vertical interconnect (18) may have a coefficient of thermal expansion (CTE) that is greater than a CTE of the dielectric layer (16) to facilitate 3D-integration.

    IN-SITU MONITORING STRUCTURES AND METHODS OF USE IN SEMICONDUCTOR PROCESSING
    2.
    发明申请
    IN-SITU MONITORING STRUCTURES AND METHODS OF USE IN SEMICONDUCTOR PROCESSING 审中-公开
    半导体工艺中的原位监测结构和使用方法

    公开(公告)号：WO2017160344A1

    公开(公告)日：2017-09-21

    申请号：PCT/US2016/057075

    申请日：2016-10-14

    Applicant: RAYTHEON COMPANY

    Inventor： KILCOYNE, Sean P. ,  EMERSON, Robert M. ,  LIGUORI, Michael V.

    IPC: H01L21/66 ,  B24B37/013 ,  B24B37/04 ,  B24B49/12

    Abstract: Systems and methods of in-situ calibration of semiconductor material layer deposition and removal processes are disclosed. Sets of test structures including one or more calibration vias or posts are used to precisely monitor processes such as plating and polishing, respectively. Known (e.g., empirically determined) relationships between the test structure features and product feature enable monitoring of wafer processing progress. Optical inspection of the calibration feature(s) during processing cycles permits dynamic operating condition adjustments and precise cessation of processing when desired product feature characteristics have been achieved.

    Abstract translation: 公开了半导体材料层沉积和去除工艺的原位校准系统和方法。 包括一个或多个校准过孔或柱子的测试结构组分别用于精确监控诸如电镀和抛光的过程。 测试结构特征和产品特征之间的已知（例如，经验确定的）关系使得能够监测晶片处理进展。 在处理周期内对校准特征进行光学检测，可以实现动态操作条件调整，并在达到所需产品特征特征时精确停止加工。

    METHOD OF WAFER BONDING OF DISSIMILAR THICKNESS DIE
    6.
    发明申请
    METHOD OF WAFER BONDING OF DISSIMILAR THICKNESS DIE 审中-公开

    公开(公告)号：WO2018191104A1

    公开(公告)日：2018-10-18

    申请号：PCT/US2018/026337

    申请日：2018-04-05

    Applicant: RAYTHEON COMPANY

    Inventor： KILCOYNE, Sean P. ,  MILLER, Eric R.

    IPC: H01L21/683 ,  H01L23/31

    Abstract: Methods, assemblies, and equipment are described for bonding one or more die (100a-100c) that may be of dissimilar thickness to a wafer. The die may be fabricated and singulated with a planarized oxide layer (114a) protecting from wafer dicing and handling debris one or more metallized post structures (112a-112c) connecting to an integrated circuit. Face sides (16a-106c) of the die are bonded to a first handle wafer (118), such that the respective post structures are aligned in a common plane. The substrate material back sides (108a-108c) of the bonded die are then thinned to a uniform thickness and bonded to a second handle wafer. The assembly may then be flipped, and the first handle wafer and protective layer including potential dicing and handling debris removed. The post structures are revealed, resulting in a composite wafer assembly including the second handle and one or more uniformly thinned die mounted thereto.

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