公开(公告)号：EP0408263A3

公开(公告)日：1992-03-18

申请号：EP90307409.4

申请日：1990-07-06

Applicant: RAYTHEON COMPANY

Inventor： Spencer, George R. ,  Skinner, Malcolm E. ,  Thompson, Bernard J. ,  Sullivan, Philip L.

IPC: G01S13/68 ,  G01S13/44

CPC classification number: G01S13/4436 ,  G01S13/685

Abstract: A method of processing in a two-channel monopulse receiver and processor includes the steps of:
(a) forming (17, 19, 21) composite signals equal to [S + (p + jy)] and [S - (p +jy)] where S is a monopulse sum signal and p and y are, respectively, pitch and yaw error signals; (b) alternately passing the composite signals through a two-channel amplifier (25A, 25B); and (c) separateing (29, 31, 33) the components in the resulting amplified composite signals for conventional monopulse processing and smoothing to eliminate the effects of any imbalance (in phase or amplitude) between the channels in the two-channel amplifier (25A, 25B).

公开(公告)号：EP0369660A2

公开(公告)日：1990-05-23

申请号：EP89311439.7

申请日：1989-11-06

Applicant: RAYTHEON COMPANY

Inventor： Galani, Zvi ,  Skinner, Malcolm E. ,  Chiesa, John A.

IPC: H03L7/185 ,  H03L7/107

CPC classification number: H03L7/10 ,  H03L7/185

Abstract: A phase lock/frequency control loop includes a voltage-­controlled oscillator (10) operating within a predetermined microwave frequency band and phase-locked to a reference oscillator (24) operating at a reference frequency below microwave frequencies. An offset loop signal is developed by an offset mixer (12) heterodyning the voltage-controlled oscillator (10) output signal with an offset microwave signal from an offset generator (14) whose frequency is located at the center of the predetermined microwave frequency band of the voltage controlled oscillator (10) to form a signal at an intermediate frequency (I.F.) within the frequency range of a programmable digital frequency divider (20). A phase/frequency detector (26) produces an error signal having a magnitude representative of the difference between the output from the divider (20) and a reference signal from a reference oscillator (24). The polarities of the error signal supplied, through an amplifier (30) and filter (32) to the voltage controlled oscillator (10) are set in accordance with whether the frequency commanded by a decoder (22) controlling the divider (20) is above or below the offset frequency. The signal frequency offset technique increases the frequency range of the indirect frequency synthesizer to twice the highest operating frequency of the programmable digital frequency divider.

Abstract translation: 锁相/频率控制回路包括在预定的微波频带内工作的压控振荡器（10），并锁相到以低于微波频率的参考频率工作的参考振荡器（24）。 偏移混合器（12）通过偏置混频器（12）来开发偏移混频器（12），该偏移混频器（12）利用来自偏移发生器（14）的偏移微波信号来对压控振荡器（10）输出信号进行外差，该偏移发生器（14）的频率位于预定微波频带的中心 所述压控振荡器（10）在可编程数字分频器（20）的频率范围内形成中频（IF）的信号。 相位/频率检测器（26）产生具有表示来自分频器（20）的输出与来自参考振荡器（24）的参考信号之间的差的幅度的误差信号。 根据由控制分频器（20）的解码器（22）指令的频率是否高于，通过放大器（30）和滤波器（32）提供给压控振荡器（10）的误差信号的极性被设定 或低于偏移频率。 信号频率偏移技术将间接频率合成器的频率范围提高到可编程数字分频器的最高工作频率的两倍。

公开(公告)号：EP0369660A3

公开(公告)日：1991-04-10

申请号：EP89311439.7

申请日：1989-11-06

Applicant: RAYTHEON COMPANY

Inventor： Galani, Zvi ,  Skinner, Malcolm E. ,  Chiesa, John A.

IPC: H03L7/185 ,  H03L7/107

CPC classification number: H03L7/10 ,  H03L7/185

Abstract: A phase lock/frequency control loop includes a voltage-­controlled oscillator (10) operating within a predetermined microwave frequency band and phase-locked to a reference oscillator (24) operating at a reference frequency below microwave frequencies. An offset loop signal is developed by an offset mixer (12) heterodyning the voltage-controlled oscillator (10) output signal with an offset microwave signal from an offset generator (14) whose frequency is located at the center of the predetermined microwave frequency band of the voltage controlled oscillator (10) to form a signal at an intermediate frequency (I.F.) within the frequency range of a programmable digital frequency divider (20). A phase/frequency detector (26) produces an error signal having a magnitude representative of the difference between the output from the divider (20) and a reference signal from a reference oscillator (24). The polarities of the error signal supplied, through an amplifier (30) and filter (32) to the voltage controlled oscillator (10) are set in accordance with whether the frequency commanded by a decoder (22) controlling the divider (20) is above or below the offset frequency. The signal frequency offset technique increases the frequency range of the indirect frequency synthesizer to twice the highest operating frequency of the programmable digital frequency divider.

公开(公告)号：EP0408263A2

公开(公告)日：1991-01-16

申请号：EP90307409.4

申请日：1990-07-06

Applicant: RAYTHEON COMPANY

Inventor： Spencer, George R. ,  Skinner, Malcolm E. ,  Thompson, Bernard J. ,  Sullivan, Philip L.

IPC: G01S13/68 ,  G01S13/44

CPC classification number: G01S13/4436 ,  G01S13/685

Abstract: A method of processing in a two-channel monopulse receiver and processor includes the steps of:

(a) forming (17, 19, 21) composite signals equal to [S + (p + jy)] and [S - (p +jy)] where S is a monopulse sum signal and p and y are, respectively, pitch and yaw error signals;
(b) alternately passing the composite signals through a two-channel amplifier (25A, 25B); and (c) separateing (29, 31, 33) the components in the resulting amplified composite signals for conventional monopulse processing and smoothing to eliminate the effects of any imbalance (in phase or amplitude) between the channels in the two-channel amplifier (25A, 25B).

Abstract translation: 一种在双通道单脉冲接收机和处理器中的处理方法包括以下步骤：（a）形成等于[S +（p + jy）]和[S - （p + jy）]的复合信号（17,19,21） ）]其中S是单脉冲和信号，p和y分别是俯仰和偏航误差信号; （b）交替地将复合信号通过双通道放大器（25A，25B）; 和（c）分离（29,31,33）所得到的放大的复合信号中的分量用于常规单脉冲处理和平滑以消除双通道放大器（25A）中的通道之间的任何不平衡（相位或幅度）的影响 ，25B）。 C