公开(公告)号：KR790000799B1

公开(公告)日：1979-06-30

申请号：KR740002299

申请日：1974-04-25

Applicant: RCA CORP

Inventor： BORYS ZUK

Abstract: A differential amplifier using semiconductor amplifier, which had a characteristic of having complementary conduction, was disclosed. Common electrodes of a 1st and 2nd PNP type input transistor(11,21) having input, common, and output electrodes(base, emitter, collector), were DC conductively coupled reciprocally. The output, input, and common electrodes of 3rd and 4th NPN type transistor(12,22) were DC coupled to the common, the output electrodes of the 1st and 2nd transistor, and the ground, resp.

公开(公告)号：US3267295A

公开(公告)日：1966-08-16

申请号：US35913964

申请日：1964-04-13

Applicant: RCA CORP

Inventor： BORYS ZUK

IPC: G11C11/412 ,  G11C19/28 ,  H03K3/356

CPC classification number: H03K3/356 ,  G11C11/412 ,  G11C19/28 ,  H03K3/356104

公开(公告)号：US3252011A

公开(公告)日：1966-05-17

申请号：US35208964

申请日：1964-03-16

Applicant: RCA CORP

Inventor： BORYS ZUK

IPC: G06F7/50 ,  G06F7/502 ,  H03K19/0948 ,  H03K19/21

CPC classification number: G06F7/502 ,  H03K19/0948 ,  H03K19/215

公开(公告)号：US3217181A

公开(公告)日：1965-11-09

申请号：US22282862

申请日：1962-09-11

Applicant: RCA CORP

Inventor： BORYS ZUK

IPC: H03K19/013 ,  H03K19/086

CPC classification number: H03K19/086 ,  H03K19/013

公开(公告)号：DE1293848B

公开(公告)日：1969-04-30

申请号：DER0040387

申请日：1965-04-13

Applicant: RCA CORP

Inventor： BORYS ZUK

IPC: G11C11/412 ,  G11C19/28 ,  H03K3/356 ,  H03K19/08

Abstract: 1,106,181. Counters; shift registers. RADIO CORPORATION OF AMERICA. 29 March, 1965 [13 April, 1964], No. 13290/65. Headings G4A and G4C. [Also in Division H3] A switching circuit comprises two similar circuit branches, each branch including two series connected semi-conductor devices of one conductivity type connected between a first point and an output terminal and a further semi-conductor device of the opposite type connected between the output terminal and a second point, and three input terminals connected to the control electrodes of the devices. The circuit may be arranged as a bi-stable circuit (Fig. 1) having insulated gate field effect transistors of opposite conductivity types 30a- 30f, 20a-20f arranged such that when the voltages applied to the RESET and SET inputs 44, 46 are interchanged and a clock pulse is applied at 48 the circuit changes state giving a different output at 28, 38. Assuming the circuit is in the RESET state, i.e. outputs (1), (0) are +V, 0 respectively, then if +V and 0 are applied to the SET and RESET terminals together with a + V clock pulse at 48, transistors 20e, 20f turn on so that the 0 (earth) potential is connected to output (1). This causes transistors 30a, 20a to turn on and off respectively and since transistor 30c has already turned on, + V is connected via transistors 30a, 30c to output (0). This in turn causes transistors 30b, 20b to turn off and on respectively such that when the RESET, SET and clock pulses are removed the output potentials remain. Transistors 70a, 70b and 70c, 70d may be combined into single units each having one source and one drain and two gate electrodes. In an alternative circuit (Fig. 3, not shown) " 0 " clock pulses are used to control the circuits. The above two circuits may be arranged alternately (Fig. 5, not shown), to form a shift register. When the clock pulse goes positive + V the first type of circuits (A1, A2) read in information and when the clock pulse is zero the second type of bi-stable circuit (B1, B2), reads in the information from the preceding bi-stable stage (A1, A2). In a further gating circuit (Fig. 6), the outputs (A, B) do not change as the clock pulse is applied unless the SET and RESET inputs are interchanged during the clock pulse. With +V and 0 applied to the RESET and SET terminals and when the clock pulse is zero, transistors 70a, 70c, 70d and 80a conduct to connect +V and 0 to outputs A and B respectively. As the clock pulse is first applied at (t n , Fig. 7, not shown), transistors 70a, 70c turn off but due to charge stored in 70d the output A remains at + V, output B is also unchanged. If the SET and RESET voltages are reversed after the start of the clock pulse at (t n+ ) then transistors 70b, 80b turn on so that the output A becomes 0 volts and transistor 80a turn off, but due to the charge stored in it the output B is maintained at 0 volts. This gate circuit may be placed between the bistable circuits to form a shift register (Fig. 8, not shown). When a clock pulse is applied to this circuit the bi-stable stages (110, 112, 114) read in the information from the previous stage as stored by the intermediate gate circuit (116 or 118).